TMP86C993XB(EYZ) Toshiba, TMP86C993XB(EYZ) Datasheet - Page 118

• Manufacturer Part Number: TMP86C993XB(EYZ)
• Description: EMULATION CHIP FOR TMP86F SSOP
• Manufacturer: Toshiba
• Series: -r

Specifications of TMP86C993XB(EYZ)

• Accessory Type: Adapter
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: TMP86F SSOP
• Other names: TMP86C993XB; TMP86C993XB

11.3
Function
11.3.2
11.3.3
TC4CR<TC4S>
Internal
Source Clock
Counter
TTREG4
INTTC4 interrupt request
TTREG4
INTTC4 interrupt request
TC4CR<TC4S>
TC4 pin input
Counter
When a match between the up-counter and the TTREGj value is detected, an INTTCj interrupt is generated and
the up-counter is cleared. After being cleared, the up-counter restarts counting at the falling edge of the input
pulse to the TCj pin. Two machine cycles are required for the low- or high-level pulse input to the TCj pin.
Therefore, a maximum frequency to be supplied is fc/2
in the SLOW1/2 or SLEEP1/2 mode.
and the TTREGj value is detected, the logic level output from the PDOj pin is switched to the opposite state and
the up-counter is cleared. The INTTCj interrupt request is generated at the time. The logic state opposite to the
timer F/Fj logic level is output from the PDOj pin. An arbitrary value can be set to the timer F/Fj by TCjCR<TFFj>.
Upon reset, the timer F/Fj value is initialized to 0.
Note 1: In the event counter mode, fix TCjCR<TFFj> to 0. If not fixed, the PDOj, PWMj and PPGj pins may output
Note 2: In the event counter mode, do not change the TTREGj setting while the timer is running. Since TTREGj is
Note 3: j = 3, 4
In the 8-bit event counter mode, the up-counter counts up at the falling edge of the input pulse to the TCj pin.
This mode is used to generate a pulse with a 50% duty cycle from the PDOj pin.
In the PDO mode, the up-counter counts up using the internal clock. When a match between the up-counter
To use the programmable divider output, set the output latch of the I/O port to 1.
8-Bit Event Counter Mode (TC3, 4)
8-Bit Programmable Divider Output (PDO) Mode (TC3, 4)
pulses.
not in the shift register configuration in the event counter mode, the new value programmed in TTREGj is in
effect immediately after the programming. Therefore, if TTREGj is changed while the timer is running, an
expected operation may not be obtained.
Figure 11-3 8-Bit Event Counter Mode Timing Chart (TC4)
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Figure 11-2 8-Bit Timer Mode Timing Chart (TC4)
0
n
n
1
1
2
3
2
Match detect
Match detect
Page 104
n-1
n-1
n 0
n 0
4
Counter clear
Hz in the NORMAL1/2 or IDLE1/2 mode, and fs/2
Counter
clear
1
1
2
2
Match detect
Match detect
n-1
n-1
n
n
0
0
Counter
clear
1
Counter clear
1
2
TMP86FH92DMG
2
0
0
4
Hz