TMP86C993XB(EYZ) Toshiba, TMP86C993XB(EYZ) Datasheet - Page 45

• Manufacturer Part Number: TMP86C993XB(EYZ)
• Description: EMULATION CHIP FOR TMP86F SSOP
• Manufacturer: Toshiba
• Series: -r

Specifications of TMP86C993XB(EYZ)

• Accessory Type: Adapter
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: TMP86F SSOP
• Other names: TMP86C993XB; TMP86C993XB

2.3.2
2.3.3
2.3.4
Instruction
execution
Internal reset
Note 1: Address “a” is on-chip RAM (WDTCR1<ATAS> = “1”) space, DBR or SFR area.
Note 2: During reset release, reset vector “r” is read out, and an instruction at address “r” is fetched and decoded.
from the on-chip RAM (when WDTCR1<ATAS> is set to “1”), DBR or SFR area, address trap reset will be
generated. The reset time is maximum 24/fc[s] (1.5μs at 16.0 MHz).
CPU. (The oscillation is continued without stopping.)
RESET
Address trap reset
Watchdog timer reset
System clock reset
If the CPU should start looping for some cause such as noise and an attempt be made to fetch an instruction
Refer to Section “Watchdog Timer”.
If the condition as follows is detected, the system clock reset occurs automatically to prevent dead lock of the
The reset time is maximum 24/fc[s] (1.5 μs at 16.0 MHz).
Note:The operating mode under address trapped is alternative of reset or interrupt. The address trap area is
-
-
-
alternative.
In case of clearing SYSCR2<XEN> and SYSCR2<XTEN> simultaneously to “0”.
In case of clearing SYSCR2<XEN> to “0”, when the SYSCR2<SYSCK> is “0”.
In case of clearing SYSCR2<XEN>to "1"when the SYSCR2<XTEN> is “0”.
VDD
JP a
Address trap is occurred
Figure 2-16 Address Trap Reset
maximum 24/fc [s]
Figure 2-15 Reset Circuit
Warming up circuit
Malfunction reset
output circuit
Page 31
4/fc to 12/fc [s]
Internal reset
Watchdog timer reset
Address trap reset
System clock reset
Voltage detection 1
Voltage detection 2
Power on reset
Trimming data reset
Reset release
16/fc [s]
TMP86FH92DMG
Instruction at address r