TMP86C993XB(EYZ) Toshiba, TMP86C993XB(EYZ) Datasheet - Page 96

• Manufacturer Part Number: TMP86C993XB(EYZ)
• Description: EMULATION CHIP FOR TMP86F SSOP
• Manufacturer: Toshiba
• Series: -r

Specifications of TMP86C993XB(EYZ)

• Accessory Type: Adapter
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: TMP86F SSOP
• Other names: TMP86C993XB; TMP86C993XB

10.2
Timer/Counter Control
Timer Register
10.2
TC1DRA
(0011H, 0010H)
TC1DRB
(0013H, 0012H)
TimerCounter 1 Control Register
MCAP1
MPPG1
ACAP1
METT1
TC1CK
(0014H)
TC1CR
TC1M
TC1S
TFF1
(TC1DRA and TC1DRB).
The TimerCounter 1 is controlled by the TimerCounter 1 control register (TC1CR) and two 16-bit timer registers
Note 1: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz]
Note 2: The timer register consists of two shift registers. A value set in the timer register becomes valid at the rising edge of the
Timer/Counter Control
Timer F/F1 control
Auto capture control
Pulse width measurement
mode control
External trigger timer
mode control
PPG output control
TC1 start control
TC1 source clock select
[Hz]
TC1 operating mode se-
lect
TFF1
first source clock pulse that occurs after the upper byte (TC1DRAH and TC1DRBH) is written. Therefore, write the lower
byte and the upper byte in this order (it is recommended to write the register with a 16-bit access instruction). Writing only
the lower byte (TC1DRAL and TC1DRBL) does not enable the setting of the timer register.
15
7
14
MCAP1
MPPG1
ACAP1
METT1
6
(Initial value: 1111 1111 1111 1111)
(Initial value: 1111 1111 1111 1111)
13
TC1DRAH (0011H)
TC1DRBH (0013H)
5
0: Clear
0 : Auto-capture disable
0 :Double edge capture
0 : Trigger start
0 : Continuous pulse generation
00: Stop and counter clear
01: Command start
10: Rising edge start
(Ex-trigger/Pulse/PPG)
Rising edge count (Event)
Positive logic count (Window)
11: Falling edge start
(Ex-trigger/Pulse/PPG)
Falling edge count (Event)
Negative logic count (Window)
00: Timer/external trigger timer/event counter mode
01: Window mode
10: Pulse width measurement mode
11: PPG (Programmable pulse generate) output mode
00
01
10
11
12
TC1S
11
4
10
DV7CK = 0
3
fc/2
fc/2
fc/2
TC1CK
11
7
3
Page 82
9
NORMAL1/2, IDLE1/2 mode
2
8
External clock (TC1 pin input)
1
7
Timer
Read/Write (Write enabled only in the PPG output mode)
TC1M
O
O
-
-
6
1: Set
1 : Auto-capture enable
1 : Single edge capture
1 : Trigger start and stop
1 : One-shot
Extrig-
0
ger
O
O
O
DV7CK = 1
-
fs/2
fc/2
fc/2
5
Read/Write
(Initial value: 0000 0000)
3
7
3
Event
TC1DRAL (0010H)
TC1DRBL (0012H)
O
O
O
-
Read/Write
4
Win-
dow
O
O
O
-
3
TMP86FH92DMG
Divider
Pulse
DV9
DV5
DV1
O
O
O
-
2
SLOW,
SLEEP
mode
PPG
fs/2
O
O
O
O
-
-
1
3
R/W
R/W
R/W
R/W
R/W
0