TMP86C993XB(EYZ) Toshiba, TMP86C993XB(EYZ) Datasheet - Page 53

• Manufacturer Part Number: TMP86C993XB(EYZ)
• Description: EMULATION CHIP FOR TMP86F SSOP
• Manufacturer: Toshiba
• Series: -r

Specifications of TMP86C993XB(EYZ)

• Accessory Type: Adapter
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: TMP86F SSOP
• Other names: TMP86C993XB; TMP86C993XB

3.3.2
Note 1: a: Return address, b: Entry address, c: Address which RETI instruction is stored
Note 2: On condition that interrupt is enabled, it takes 38/fc [s] or 38/fs [s] at maximum (If the interrupt latch is set at the first
Interrupt
request
Interrupt
latch (IL)
IMF
Execute
instruction
PC
SP
Figure 3-1 Timing Chart of Interrupt Acceptance/Return Interrupt Instruction
service program
level of current servicing interrupt is requested.
acceptable interrupt sources are selectively enabled by the individual interrupt enable flags.
before setting IMF to “1”. As for non-maskable interrupt, keep interrupt service shorten compared with length
between interrupt requests; otherwise the status cannot be recovered as non-maskable interrupt would simply
nested.
IMF) are automatically saved on the stack, but the accumulator and others are not. These registers are saved by
software if necessary. When multiple interrupt services are nested, it is also necessary to avoid using the same
data memory area for saving registers. The following methods are used to save/restore the general-purpose reg-
isters.
1-machine cycle
Saving/restoring general-purpose registers
machine cycle on 10 cycle instruction) to start interrupt acceptance processing since its interrupt latch is set.
Example: Correspondence between vector table address for INTTBT and the entry address of the interrupt
A maskable interrupt is not accepted until the IMF is set to “1” even if the maskable interrupt higher than the
In order to utilize nested interrupt service, the IMF is set to “1” in the interrupt service program. In this case,
To avoid overloaded nesting, clear the individual interrupt enable flag whose interrupt is currently serviced,
During interrupt acceptance processing, the program counter (PC) and the program status word (PSW, includes
a − 1
instruction
Execute
a
FFF0H
FFF1H
Figure 3-2 Vector Table Address and Entry Address
Vector table address
a + 1
n
D2H
03H
Interrupt acceptance
a
n − 1
Vector
n − 2
Page 39
b
b + 1
b + 2
instruction
Execute
b + 3
n - 3
D203H
D204H
c + 1
Entry address
Interrupt service task
0FH
06H
n − 2 n − 1
c + 2
Execute RETI instruction
Interrupt
service
program
TMP86FH92DMG
a
a + 1
n
a + 2