TMP86C993XB(EYZ) Toshiba, TMP86C993XB(EYZ) Datasheet - Page 167

• Manufacturer Part Number: TMP86C993XB(EYZ)
• Description: EMULATION CHIP FOR TMP86F SSOP
• Manufacturer: Toshiba
• Series: -r

Specifications of TMP86C993XB(EYZ)

• Accessory Type: Adapter
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: TMP86F SSOP
• Other names: TMP86C993XB; TMP86C993XB

15.5.3.2
to low will, in the first place, invalidate a clock pulse of another master device which generates a high-level
clock pulse.
even if there are two or more masters on the same bus.
level. After detecting this situation, Master 2 resets counting a clock pulse in the high level and sets the SCL
pin to the low level.
Since Master 2 holds the SCL line of the bus at the low level, Master 1 waits for counting a clock pulse in
the high level. After Master 2 sets a clock pulse to the high level at point “c” and detects the SCL line of the
bus at the high level, Master 1 starts counting a clock pulse in the high level. Then, the master, which has
finished the counting a clock pulse in the high level, pulls down the SCL pin to the low level.
In the I
The serial bus interface circuit has a clock synchronization function. This function ensures normal transfer
The example explains clock synchronization procedures when two masters simultaneously exist on a bus.
As Master 1 pulls down the SCL pin to the low level at point “a”, the SCL line of the bus becomes the low
Master 1 finishes counting a clock pulse in the low level at point “b” and sets the SCL pin to the high level.
SCL pin (Master 1)
SCL pin (Master 2)
SCL (Bus)
Clock synchronization
Note 1: fc = High-frequency clock
Note 2: tcyc = 4/fc (in NORMAL mode, IDLE mode)
2
C bus, in order to drive a bus with a wired AND, a master device which pulls down a clock pulse
t SCKL , t SCKH > 4 tcyc
t LOW = 2 /fc
t HIGH = 2 /fc + 8/fc
fscl = 1/( t LOW + t HIGH)
t SCKL
n
n
Figure 15-4 Clock Synchronization
t HIGH
t SCKH
Figure 15-3 Clock Source
a
Count restart
t LOW
Page 153
SCK (Bits2 to 0 in the SBICRA)
b
Wait
000
001
010
011
100
101
110
c
1/fscl
Count start
Count reset
10
n
4
5
6
7
8
9
TMP86FH92DMG