TMP86C993XB(EYZ) Toshiba, TMP86C993XB(EYZ) Datasheet - Page 85

• Manufacturer Part Number: TMP86C993XB(EYZ)
• Description: EMULATION CHIP FOR TMP86F SSOP
• Manufacturer: Toshiba
• Series: -r

Specifications of TMP86C993XB(EYZ)

• Accessory Type: Adapter
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: TMP86F SSOP
• Other names: TMP86C993XB; TMP86C993XB

Watchdog Timer Control Register 1
8.2.2
Watchdog Timer Control Register 2
WDTCR1
WDTCR2
(0034H)
(0035H)
Note 1: After clearing WDTOUT to “0”, the program cannot set it to “1”.
Note 2: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *: Don’t care
Note 3: WDTCR1 is a write-only register and must not be used with any of read-modify-write instructions. If WDTCR1 is read, a
Note 4: To activate the STOP mode, disable the watchdog timer or clear the counter immediately before entering the STOP mode.
Note 5: To clear WDTEN, set the register in accordance with the procedures shown in “8.2.3 Watchdog Timer Disable”.
“1” during reset, the watchdog timer is enabled automatically after the reset release.
Watchdog Timer Enable
Note 1: The disable code is valid only when WDTCR1<WDTEN> = 0.
Note 2: *: Don’t care
Note 3: The binary counter of the watchdog timer must not be cleared by the interrupt task.
Note 4: Write the clear code 4EH using a cycle shorter than 3/4 of the time set in WDTCR1<WDTT>.
Setting WDTCR1<WDTEN> to “1” enables the watchdog timer. Since WDTCR1<WDTEN> is initialized to
WDTCR2
don’t care is read.
After clearing the counter, clear the counter again immediately after the STOP mode is inactivated.
7
7
WDTOUT
WDTEN
WDTT
6
Write
Watchdog timer control code
6
Watchdog timer enable/disable
Watchdog timer detection time [s]
Watchdog timer output select
(ATAS)
5
5
4
(ATOUT)
4
4EH: Clear the watchdog timer binary counter (Clear code)
B1H: Disable the watchdog timer (Disable code)
D2H: Enable assigning address trap area
Others: Invalid
3
WDTEN
Page 71
3
0: Disable (Writing the disable code to WDTCR2 is required.)
1: Enable
0: Interrupt request
1: Reset request
00
01
10
11
2
2
DV7CK = 0
WDTT
1
2
2
2
2
25
23
19
21
/fc
/fc
/fc
fc
NORMAL1/2 mode
1
0
WDTOUT
(Initial value: **** ****)
DV7CK = 1
0
2
2
2
2
17
15
13
11
/fs
/fs
/fs
/fs
(Initial value: **11 1001)
TMP86FH92DMG
SLOW1/2
mode
2
2
2
2
17
11
15
13
/fs
/fs
fs
fs
Write
Write
Write
Write
only
only
only
only