TMP86C993XB(EYZ) Toshiba, TMP86C993XB(EYZ) Datasheet - Page 157

• Manufacturer Part Number: TMP86C993XB(EYZ)
• Description: EMULATION CHIP FOR TMP86F SSOP
• Manufacturer: Toshiba
• Series: -r

Specifications of TMP86C993XB(EYZ)

• Accessory Type: Adapter
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: TMP86F SSOP
• Other names: TMP86C993XB; TMP86C993XB

14.5.2
Table 14-5 Transfer Format Details when CPHA = 1
Figure 14-3 shows a transfer format when CPHA = 1.
CPHA = 1 format
SCLK Cycle
SCLK
(CPOL = 0)
SCLK
(CPOL = 1)
MOSI
MISO
SS
SEF
・ In master mode, transfer is initiated by writing new data to the SEDR register. The new data changes
・ In slave mode, unlike in the case of CPHA = 0 format, data can be written to the SEDR (SEI Data
CPOL=0
CPOL=1
state on the MOSI pin at the first edge of the shift clock. Use BOS (SECR<BOS>) to select whether
the data should be shifted out beginning with the MSB or LSB.
Register) regardless of whether the SS pin is “L” or “H”. In both master and slave modes, the SEF flag
(SESR<SEF>) is set after the last shift cycle. Writing data to the SEDR register while data transfer is
in progress causes collision of writes. Therefore, wait until the SEF flag is set before writing new data
to the SEDR register.
Figure 14-3 Transfer Format When CPHA = 1
Communicating (IDLE)
SCLK Level when Not
“H” level
“L” level
1
2
Rising edge of transfer clock
Falling edge of transfer clock
3
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4
Data Shift
5
6
Falling edge of transfer clock
Rising edge of transfer clock
7
8
Data Sampling
Internal
shift clock
TMP86FH92DMG