TMP86C993XB(EYZ) Toshiba, TMP86C993XB(EYZ) Datasheet - Page 209

• Manufacturer Part Number: TMP86C993XB(EYZ)
• Description: EMULATION CHIP FOR TMP86F SSOP
• Manufacturer: Toshiba
• Series: -r

Specifications of TMP86C993XB(EYZ)

• Accessory Type: Adapter
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: TMP86F SSOP
• Other names: TMP86C993XB; TMP86C993XB

Note 7: If an error occurs during the reception of a password address or a password string, TMP86FH92DMG stops UART com-
Note 8: Do not write only the address from FFE0H to FFFFH when all flash memory data is the same. If only these area are written,
Note 9: To rewrite data to Flash memory addresses at which data (including FFH) is already written, make sure to erase the
Description of the flash memory writing mode
munication and enters the halt condition. In this case, initialize TMP86FH92DMG by the RESET pin and reactivate the
serial PROM mode.
the subsequent operation can not be executed due to password error.
existing data by "sector erase" or "chip erase" before rewriting data.
1. The 1st byte of the received data contains the matching data. When the serial PROM mode is activated,
2. When receiving the matching data (5AH), the device transmits an echo back data (5AH) as the second
3. The 3rd byte of the received data contains the baud rate modification data. The five types of baud rate
4. Only when the 3rd byte of the received data contains the baud rate modification data corresponding to
5. The 5th byte of the received data contains the command data (30H) to write the flash memory.
6. When the 5th byte of the received data contains the operation command data shown in Table 19-6, the
7. The 7th byte contains the data for 15 to 8 bits of the password count storage address. When the data
8. The 9th byte contains the data for 7 to 0 bits of the password count storage address. When the data
9. The 11th byte contains the data for 15 to 8 bits of the password comparison start address. When the
10. The 13th byte contains the data for 7 to 0 bits of the password comparison start address. When the data
11. The 15th through m’th bytes contain the password data. The number of passwords becomes the data
12. The m’th + 1 through n’th - 2 bytes of the received data contain the binary data in the Intel Hex format.
TMP86FH92DMG (hereafter called device), waits to receive the matching data (5AH). Upon reception
of the matching data, the device automatically adjusts the UART’s initial baud rate to 9600 bps.
byte data to the external controller. If the device can not recognize the matching data, it does not transmit
the echo back data and waits for the matching data again with automatic baud rate adjustment. There-
fore, the external controller should transmit the matching data repeatedly till the device transmits an
echo back data. The transmission repetition count varies depending on the frequency of device. For
details, refer to Table 19-5.
modification data shown in Table 19-4 are available. Even if baud rate is not modified, the external
controller should transmit the initial baud rate data (28H: 9600 bps).
the device's operating frequency, the device echoes back data the value which is the same data in the
4th byte position of the received data. After the echo back data is transmitted, baud rate modification
becomes effective. If the 3rd byte of the received data does not contain the baud rate modification data,
the device enters the halts condition after sending 3 bytes of baud rate modification error code (62H).
device echoes back the value which is the same data in the 6th byte position of the received data (in
this case, 30H). If the 5th byte of the received data does not contain the operation command data, the
device enters the halt condition after sending 3 bytes of the operation command error code (63H).
received with the 7th byte has no receiving error, the device does not send any data. If a receiving error
or password error occurs, the device does not send any data and enters the halt condition.
received with the 9th byte has no receiving error, the device does not send any data. If a receiving error
or password error occurs, the device does not send any data and enters the halt condition.
data received with the 11th byte has no receiving error, the device does not send any data. If a receiving
error or password error occurs, the device does not send any data and enters the halt condition.
received with the 13th byte has no receiving error, the device does not send any data. If a receiving
error or password error occurs, the device does not send any data and enters the halt condition.
(N) stored in the password count storage address. The external password data is compared with N-byte
data from the address specified by the password comparison start address. The external controller should
send N-byte password data to the device. If the passwords do not match, the device enters the halt
condition without returning an error code to the external controller. If the addresses from FFE0H to
FFFFH are filled with “FFH”, the passwords are not compared because the device is considered as a
blank product.
No received data is echoed back to the external controller. After receiving the start mark (3AH for “:”)
in the Intel Hex format, the device starts data record reception. Therefore, the received data except 3AH
is ignored until the start mark is received. After receiving the start mark, the device receives the data
record, that consists of data length, address, record type, write data and checksum. Since the device
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