TMP86C993XB(EYZ) Toshiba, TMP86C993XB(EYZ) Datasheet - Page 152

• Manufacturer Part Number: TMP86C993XB(EYZ)
• Description: EMULATION CHIP FOR TMP86F SSOP
• Manufacturer: Toshiba
• Series: -r

Specifications of TMP86C993XB(EYZ)

• Accessory Type: Adapter
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: TMP86F SSOP
• Other names: TMP86C993XB; TMP86C993XB

14.2
SEI Registers
14.2
Read-modify-write instruction are prohibited.
14.2.1
(002AH)
SECR
which are used to set up the SEI system and enable/disable SEI operation.
14.2.1.1
The SEI interface has the SEI Control Register (SECR), SEI Status Register (SESR), and SEI Data Register (SEDR)
Note 1: If mode fault detection is enabled, an interrupt is generated when the MODF flag (SESR<MODF>) is set.
Note 2: SEI operation can only be disabled after transfer is completed. Before the SEI can be used, the each Port Control Register
Note 3: Master/slave settings must be made before enabling SEI operation (This means that the SECR<MSTR> bit must first be
SEI Registers
SEI Control Register (SECR)
MODE
and Output Latch Control must be set for the SEI function (In case P0 port, P0OUTCR and P0DR).
When using the SEI as the master, set the SECR<SEE> bit to “1” (to enable SEI operation) and then place transmit data
in the SEDR register. This initiates transmission/reception.
set before setting the SECR<SEE> bit to “1”).
(1)
MODE
MSTR
CPOL
CPHA
7
SEE
BOS
SER
Transfer rate
the SEI is operating as the master.
The table below shows the relationship between settings of the SER bit and transfer bit rates when
Master mode (Transfer rate = fc/Internal clock divide ratio (unit: bps))
SEE
6
Table 14-1 SEI Transfer Rate
Mode fault detection (Note1)
SEI operation (Note2)
Bit order selection
Mode selection (Note3)
Clock polarity
Clock phase
Selects SEI transfer rate
SER
00
01
10
11
BOS
5
Internal Clock Divide Ratio of SEI
MSTR
4
16
64
4
8
CPOL
3
Page 138
0: Enables mode fault detection
1: Disables mode fault detection
It is available in Master mode only.
(Note: Make sure to set <MODE> bit to "1" for disabling Mode fault de-
tection
0: Disables SEI operation
1: Enables SEI operation
0: Transmitted beginning with the MSB (bit 7) of SEDR register
1: Transmitted beginning with the LSB (bit 0) of SEDR register
0: Sets SEI for slave
1: Sets SEI for master
0: Selects active-“H” clock. SCLK remains “L” when IDLE.
1: Selects active-“L” clock. SCLK remains “H” when IDLE.
Selects clock phase. For details, refer to Section “SEI Transfer Formats”.
00: Divide-by-4
01: Divide-by-8
10: Divide-by-16
11: Divide-by-64
CPHA
2
Transfer Rate when fc = 16 MHz
1
SER
250 kbps
4 Mbps
2 Mbps
1 Mbps
0
(Initial value: 0000 0100)
TMP86FH92DMG
R/W