TMP86C993XB(EYZ) Toshiba, TMP86C993XB(EYZ) Datasheet - Page 129

• Manufacturer Part Number: TMP86C993XB(EYZ)
• Description: EMULATION CHIP FOR TMP86F SSOP
• Manufacturer: Toshiba
• Series: -r

Specifications of TMP86C993XB(EYZ)

• Accessory Type: Adapter
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: TMP86F SSOP
• Other names: TMP86C993XB; TMP86C993XB

Example :After checking low-frequency clock oscillation stability with TC4 and 3, switching to the SLOW1 mode
11.3.9
11.3.9.1
PINTTC4:
VINTTC4:
switched between the high-frequency and low-frequency. The timer counter 3 and 4 are cascadable to form a 16-
bit TimerCounter. The warm-up counter mode has two types of mode; switching from the high-frequency to low-
frequency, and vice-versa.
Note 1: In the warm-up counter mode, fix TCiCR<TFFi> to 0. If not fixed, the PDOi, PWMi and PPGi pins may output
Note 2: In the warm-up counter mode, only upper 8 bits of the timer register TTREG4 and 3 are used for match
Note 3: i = 3, 4
Table 11-8 Setting Time of Low-Frequency Warm-Up Counter Mode (fs = 32.768 kHz)
In this mode, the warm-up period time is obtained to assure oscillation stability when the system clocking is
Warm-Up Counter Mode
obtained. Before starting the timer, set SYSCR2<XTEN> to 1 to oscillate the low-frequency clock. When a
match between the up-counter and the timer register (TTREG4, 3) value is detected after the timer is started
by setting TC4CR<TC4S> to 1, the counter is cleared by generating the INTTC4 interrupt request. After
stopping the timer in the INTTC4 interrupt service routine, set SYSCR2<SYSCK> to 1 to switch the system
clock from the high-frequency to low-frequency, and then clear of SYSCR2<XEN> to 0 to stop the high-
frequency clock.
(NORMAL1 → NORMAL2 → SLOW2 → SLOW1)
In this mode, the warm-up period time from a stop of the low-frequency clock fs to oscillation stability is
Low-Frequency Warm-up Counter Mode
pulses.
detection and lower 8 bits are not used.
SET
LD
LD
LDW
DI
SET
EI
SET
:
CLR
SET
CLR
RETI
:
DW
Minimum Time Setting
(TTREG4, 3 = 0100H)
7.81 ms
(SYSCR2).6
(TC3CR), 43H
(TC4CR), 05H
(TTREG3), 8000H
(EIRH). 7
(TC4CR).3
:
(TC4CR).3
(SYSCR2).5
(SYSCR2).7
:
PINTTC4
; SYSCR2<XTEN> ← 1
; Sets TFF3=0, source clock fs, and 16-bit mode.
; Sets TFF4=0, and warm-up counter mode.
; Sets the warm-up time.
; (The warm-up time depends on the oscillator characteristic.)
; IMF ← 0
; Enables the INTTC4.
; IMF ← 1
; Starts TC4 and 3.
; Stops TC4 and 3.
; SYSCR2<SYSCK> ← 1
; (Switches the system clock to the low-frequency clock.)
; SYSCR2<XEN> ← 0 (Stops the high-frequency clock.)
; INTTC4 vector table
Page 115
Maximum Time Setting
(TTREG4, 3 = FF00H)
1.99 s
TMP86FH92DMG