TMP86C993XB(EYZ) Toshiba, TMP86C993XB(EYZ) Datasheet - Page 124

• Manufacturer Part Number: TMP86C993XB(EYZ)
• Description: EMULATION CHIP FOR TMP86F SSOP
• Manufacturer: Toshiba
• Series: -r

Specifications of TMP86C993XB(EYZ)

• Accessory Type: Adapter
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: TMP86F SSOP
• Other names: TMP86C993XB; TMP86C993XB

11.3
Function
11.3.6
11.3.7
TC4CR<TC4S>
TTREG3
(Lower byte)
TTREG4
(Upper byte)
INTTC4 interrupt request
Internal
source clock
Counter
TimerCounter 3 and 4 are cascadable to form the 16-bit PWM signal generator.
level output from the timer F/F4 is switched to the opposite state. The counter continues counting. The logic level
output from the timer F/F4 is switched to the opposite state again by the counter overflow, and the counter is
cleared. The INTTC4 interrupt is generated at this time.
generated. Upon reset, the timer F/F4 is cleared to 0.
and 4 are cascadable to form a 16-bit event counter.
timer is started by setting TC4CR<TC4S> to 1, an INTTC4 interrupt is generated and the up-counter is cleared.
machine cycles are required for the low- or high-level pulse input to the TC3 pin.
2
order in the timer register. (Programming only the upper or lower byte should not be attempted.)
Note 1: In the event counter mode, fix TCjCR<TFFj> to 0. If not fixed, the PDOj, PWMj and PPGj pins may output pulses.
Note 2: In the event counter mode, do not change the TTREGj setting while the timer is running. Since TTREGj is not in the
Note 3: j = 3, 4
frequency to be supplied is fc/2
SLEEP1/2 mode.
4
This mode is used to generate a pulse-width modulated (PWM) signals with up to 16 bits of resolution. The
The counter counts up using the internal clock or external clock.
When a match between the up-counter and the timer register (PWREG3, PWREG4) value is detected, the logic
Since the initial value can be set to the timer F/F4 by TC4CR<TFF4>, positive and negative pulses can be
(The logic level output from the PWM4 pin is the opposite to the timer F/F4 logic level.)
In the event counter mode, the up-counter counts up at the falling edge to the TC3 pin. The TimerCounter 3
When a match between the up-counter and the timer register (TTREG3, TTREG4) value is detected after the
After being cleared, the up-counter restarts counting at the falling edge of the input pulse to the TC3 pin. Two
Therefore, a maximum frequency to be supplied is fc/2
Two machine cycles are required for the high- or low-level pulse input to the TC3 pin. Therefore, a maximum
in the SLOW1/2 or SLEEP1/2 mode. Program the lower byte (TTREG3), and upper byte (TTREG4) in this
16-Bit Event Counter Mode (TC3 and 4)
16-Bit Pulse Width Modulation (PWM) Output Mode (TC3 and 4)
shift register configuration in the event counter mode, the new value programmed in TTREGj is in effect immediately
after the programming. Therefore, if TTREGj is changed while the timer is running, an expected operation may not be
obtained.
Figure 11-6 16-Bit Timer Mode Timing Chart (TC3 and TC4)
?
?
0
n
m
1
2
4
Hz in the NORMAL1/2 or IDLE1/2 mode, and fs/2
3
Match
detect
mn-1
Page 110
mn
0
Counter
clear
1
4
Hz in the NORMAL1/2 or IDLE1/2 mode, and fs/
2
Match
detect
mn-1
mn
0
Counter
clear
1
4
to in the SLOW1/2 or
TMP86FH92DMG
2
0