RCLXT16706FE Intel, RCLXT16706FE Datasheet
RCLXT16706FE
Specifications of RCLXT16706FE
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RCLXT16706FE Summary of contents
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... IXF6048 51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface Intel IXF6048 is a single-chip interface solution for the transport of ATM cells or HDLC frames over SONET/SDH. Intel IXF6048 can operate as a quad 51/155/622 Mbit single 2488 Mbit/s SONET/SDH processor. When configured in ATM UNI mode, it interfaces with an ATM layer device using the industry standard UTOPIA interface (Levels 3/2/1) ...
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... Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com. ...
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Contents 1.0 Pin Description ............................................................................................................................ 11 2.0 Main Features .............................................................................................................................. 93 2.1 General ............................................................................................................................... 93 2.1.1 SONET/SDH Receiver Block ................................................................................. 93 2.1.2 SONET/SDH Transmitter Block ............................................................................. 94 2.1.3 Receive ATM Cell Processor Block ....................................................................... 95 2.1.4 Transmit ATM Cell Processor ...
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Contents 4.5.1.2 Receive Side: RSOH Serial Bus .......................................................... 139 4.5.2 Higher Order Path OverHead Access.................................................................. 140 4.5.2.1 Transmit Side: TPOH Serial Bus ......................................................... 140 4.5.2.2 Receive Side: RPOH Serial Bus .......................................................... 141 4.5.3 Section (Line) Alarms, APS and Ring Bus........................................................... ...
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... Transparent Mode Functional Description .............................................................................212 9.1 Receive Direction..............................................................................................................212 9.2 Transmit Direction.............................................................................................................212 10.0 Microcontroller Interface ..........................................................................................................213 10.1 Intel Interface ....................................................................................................................213 10.2 Motorola* Interface ...........................................................................................................213 10.3 Interrupt Handling .............................................................................................................214 10.3.1 Interrupt Sources .................................................................................................214 10.3.2 Interrupt Enables .................................................................................................214 10.3.3 Interrupt Clearing .................................................................................................214 10 ...
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... Boundary Scan Register...................................................................................... 348 14.0 Package Information ................................................................................................................. 350 Figures 1 Block Diagram .............................................................................................................................. 1 2 Intel IXF6048 Application Diagram ............................................................................................. 11 3 2488 Mbit/s Line Side Interface Example ................................................................................. 101 4 Quad 155/51 Mbit/s Line Side Interface Example .................................................................... 102 5 Quad OC-12c Example: Four Independent 8-Bit Parallel TTL Interfaces ................................ 103 6 OC-48 Repeater Application ...
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Cell Rate Decoupling FIFOs in ATM-UTOPIA Multi-Channel Configuration ............................165 34 Cell Rate Decoupling FIFO in ATM-UTOPIA Single-Channel Configuration............................165 35 Four Independent ATM-UTOPIA Interfaces .............................................................................166 36 ATM-UTOPIA Multiple Physical Device Mode..........................................................................167 37 7-Word ATM Cell Structure (64-Bit UTOPIA Interface) ............................................................170 ...
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Contents 68 Receive POS-UTOPIA Interface as a Multiple PHY Device with 64-Bit Data Bus Using Port Selection (POS-UTOPIA Level 3 Mode) ................................................................. 207 69 Transmit POS-UTOPIA Interface as a Multiple PHY Device with 64-Bit Data Bus Using Port Selection (POS-UTOPIA ...
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... Tables 1 Intel IXF6048 Main Configurations .............................................................................................12 2 Intel IXF6048 Pin Diagram (Bottom View) .................................................................................. 13 3 Intel IXF6048 Pin Diagram (Bottom View) .................................................................................. 14 4 Pin Description............................................................................................................................ 15 5 PECL I/O Pin Equivalence on the Line Side Interface................................................................ 81 6 I/O Pin Equivalence on the Receive TTL Line Side Interface..................................................... 82 7 I/O Pin Equivalence on the Transmit TTL Line Side Interface ...
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Contents 44 Receive UTOPIA Single Interface Timings for the Configurations Supporting 104 MHz Operation: 32/16/8-Bit Wide Data Bus, Two Decode-Response Clock Cycles and No High-Impedance Outputs ............................................................................................. 338 45 Transmit UTOPIA Single Interface Timings for the Configurations Supporting 104 MHz ...
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... Mbit/s SONET/SDH Cell/Packet Interface — Intel IXF6048 1.0 Pin Description Figure 2. Intel IXF6048 Application Diagram Datasheet 11 ...
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... Intel IXF6048 — 51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface Table 1. Intel IXF6048 Main Configurations Operation Mode Single STS-48c/STM-16c Single STS-48/STM-16 Single STS-12/STM-4 Single STS-3/STM-1 Quad STS-12c/STM-4c Quad STS-3c/STM-1 Quad STS-1 12 Line Side Interfaces ATM/POS-UTOPIA Interfaces 1 x 16-bit PECL at 155.52 MHz 1 x 32-bit 104 MHz (UL3 32-bit TTL at 77 ...
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... Mbit/s SONET/SDH Cell/Packet Interface — Intel IXF6048 Table 2. Intel IXF6048 Pin Diagram (Bottom View TXDATA[22] TXDATA[12] 1 GND_TTL GND_TTL TXDATA_1[6] TXPRTY_2 TXDAT_0[12] TXDATA_2[6] TXDATA_1[4] TXDATA[17] TXDATA[15] 2 GND_TTL GND_TTL TXSOF_3 TXDATA_1[1] TXDAT_0[15] TXDATA_2[1] TXDATA_1[7] TXDATA[27] TXDATA[25] TXDATA[16] 3 TXDAT_1[11] TXDATA_1[9] VDD_CORE TXDATA_1[0] TXERR_2 ...
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... Intel IXF6048 — 51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface Table 3. Intel IXF6048 Pin Diagram (Bottom View TMOW TPOWBYC TSOHINS_3 TSOH_3 TSALFR_2 GND_CORE TSOHFR_3 TRD_3 TMD_3 TXDATA[38] TRDC_3 TPOWC TSALFR_1 TSOHINS_0 TSOH_1 TXDATA[37] VDD_CORE TSOHCK_3 TRD_0 TMD_1 TMDC_3 TSALCK_1 TSALCK TSOHFR TSOHCK TSOH_0 ...
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... Receive Parallel Data Input PECL The receive PECL single parallel line side interface provides high speed connection (155.52 MHz 2,488 Mbit/s 1:16 demultiplexer. The single 16-bit PECL mode can be used when Intel IXF6048 is configured as a single STS-48c, STM-16c, STS-48, or STM-16 transceiver. ...
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... The byte position indicated by RFPI_P/N is selected by using Diff. RcvFPICnf[7:0] (global register R_FPCNF). RFPI_P/N should be active- LVPECL high for a single RPCI_P/N period. Intel IXF6048 ignores pulses on Input RFPI_P/N while “in frame” (ROOF_0 = '0'). RFPI_P/N is sampled on the rising edge of RPCI_P When frame alignment is enabled (bit RcvFBaDsbl = ‘0’ in register R_RSTC), RFPI_P have to be tied to GND_PECL and RFPI_N should be tied to VDD_PECL ...
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... TPCI_P or RPCI_P)—see T_COCNF:XmtTimRef. TPDO_P/N[15] is the MSB or first transmitted bit. Connect this pin to the MSB of the serializer/Mux device, in other words, pin[15] to the MSB through pin[0] to the LSB. For the Intel (the MSB on the Intel IXF6048) would be connected to pin[0] (the MSB ® on the Intel GD16523). ...
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... RPCI_P/N clock input in that case. Transmit Frame Position Input PECL. TFPI_P active-high frame position input providing connection to an external OC-192 SONET/SDH multiplexer. TFPI_P/N is used to align the SONET/SDH frames generated by Intel IXF6048 to an external 8-KHz system Diff. reference. Select the byte position indicated by TFPI_P/N by configuring LVPECL XmtFPICnf[7:0] (global register T_FPCNF) ...
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... MHz/38.88 MHz/19.44 MHz/8-KHz clock (OC- Output a 51.84 MHz/25.92 MHz/12.96 MHz/6.48 MHz/8-KHz clock (OC-1 When the Intel IXF6048 is configured as a single STS-3 (non- concatenated) transceiver, RSCO_1, RSCO_2, and RSCO_3 are tristated. Receive Lock Detect TTL. RLOCK_i ( the active-high Lock Detect input for channel #i. RLOCK_i indicates that the external clock recovery PLL used by channel #i is locked ...
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... Intel IXF6048 — 51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface Table 4. Pin Description (Sheet 6 of 66) Pin Name Pin Transmit 155/51 Mbit/s Differential PECL Quad 1-Bit Serial Line Side Interface TSDO_P0 AK15 TSDO_P1 AK13 TSDO_P2 AH11 TSDO_P3 AL8 TSDO_N0 AJ15 TSDO_N1 AJ13 TSDO_N2 AG11 ...
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... RSCI_Pi clock input in that case. Transmit Common Clock Input PECL. TCCI_P/N can be used as a Diff. common timing reference for each Intel IXF6048 transmit channel. LVPECL TCCI_P 155.52 MHz (STS-3c/STM- 51.84 MHz (STS-1) Input 50% duty cycle clock that provides timing for the four transmitters. ...
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... The receive TTL single parallel line side interface provides low speed connection (≤ 77.76 MHz) to 2,488 Mbit/s demultiplexers. The single 32-bit mode can be used when Intel IXF6048 is configured as a single STS-48c, STM-16c, STS-48, or STM-16 transceiver. RPDI[31:0] carries the incoming 2,488 Mbit/s data stream in 32-bit format. ...
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... Select the byte position indicated by RFPI by using RcvFPICnf[7:0] LVTTL (global register R_FPCNF). RFPI should be active-high for a single RPCI Input period. Intel IXF6048 ignores pulses on RFPI while “in frame” (ROOF = '0'). RFPI is sampled on the rising edge of RPCI. When frame alignment is enabled (bit RcvFBaDsbl = ‘0’ in register R_RSTC), RFPI have to be tied to GND ...
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... Transmit Parallel Data Output TTL The transmit TTL single parallel line side interface provides low speed connection (≤ 77.76 MHz) to 2,488 Mbit/s multiplexers. The single 32-bit mode can be used when Intel IXF6048 is configured as a single STS-48c, STM-16c, STS-48, or STM-16 transceiver. LVTTL TPDO[31:0] carry the outgoing 2,488 Mbit/s data stream in 32-bit format ...
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... Transmit Frame Position Input TTL. TFPI is an active-high frame position input providing connection to an external OC-192 SONET/SDH multiplexer. TFPI is used to align the SONET/SDH frames generated by Intel IXF6048 to an external 8-KHz system reference. Select the byte position indicated by TFPI by configuring XmtFPICnf[7:0] LVTTL (global register T_FPCNF) ...
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... The receive TTL quad parallel line side interface provides low speed connection (≤ 77.76 MHz) to 622, 155 Mbit/s demultiplexers. The quad 8-bit mode can be used when Intel IXF6048 is configured as a quad STS-12c, STM-4c, STS-3c, STM-1, STS-1, or STM-0 transceiver. RPDI_i[7: carry the incoming 622, 155 Mbit/s data stream, in byte format, for channel #i ...
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... LVTTL Receive channel #i ignores pulses on RFPI_i while “in frame” (ROOF_i = Input '0'). When Intel IXF6048 is configured as a single STS-12, STM-4, or STS-3 (non-concatenated or concatenated) transceiver, RFPI_1, RFPI_2, and RFPI_3 are unused inputs. RFPI_i is sampled on the rising edge of RPCI_i ( 3). When frame alignment is enabled (bit RcvFBaDsbl = ‘0’ in register R_RSTC), RFPI_i have to be tied to GND ...
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... Transmit Parallel Data Output TTL The transmit TTL quad parallel line side interface provides low speed connection (≤ 77.76 MHz) to 622/155/51 Mbit/s multiplexers. The quad 8-bit mode can be used when Intel IXF6048 is configured as a Quad STS-12c/STM-4c/STS-3c/STM-1/STS-1/STM-0 transceiver. TPDO_i[7: carries the outgoing 622/155/51 Mbit/s data stream in byte format for channel #i ...
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... Transmit Parallel Clock Output TTL. TPCO_i ( flow- through or divided version of TPCI_i or RPCI_i. XmtCOCnf (register T_COCNF) configures the TPCO_i ( outputs as a 77.76 MHz/38.88 MHz/19.44 MHz/8-KHz clock. When Intel IXF6048 is configured as a single STS-12/STM-4/STS-3 (non-concatenated or concatenated) transceiver, TPCO_1, TPCO_2, and TPCO_3 are tristated LVTTL ...
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... Receive Serial Data Input TTL The receive TTL quad serial line side interface provides connection to serial 51.84 Mbit/s demultiplexers. The quad serial mode can be used LVTTL when Intel IXF6048 is configured as a Quad STS-1/STM-0 transceiver. Input RSDI_i ( carries the incoming 51 Mbit/s serial data stream for channel #i. ...
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... The transmit TTL quad serial line side interface provides connection to LVTTL serial 51.84 Mbit/s demultiplexers. The quad serial mode can be used Output when Intel IXF6048 is configured as a Quad STS-1/STM-0 transceiver. TSDO_i ( carries the outgoing 51 Mbit/s serial data stream 12 mA for channel #i. ...
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... Intel IXF6048 — 51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface Table 4. Pin Description (Sheet 18 of 66) Pin Name Pin OH, Alarm, DCC and Orderwire Insertion/Extraction Ports Single PHY Mode (OH Ports Logical RSOH_0 H29 RSOH_1 K26 RSOH_2 J28 RSOH_3 G31 RSOHFR J29 RSOHCK K28 RSAL E28 ...
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... Mbit/s SONET/SDH Cell/Packet Interface — Intel IXF6048 Table 4. Pin Description (Sheet 19 of 66) Pin Name Pin TSOHCK AA3 TSAL R3 TSALFR T4 TSALCK V3 RPOH_0 E26 RPOH_1 A29 RPOH_2 B28 RPOH_3 D27 RPOHFR_0 F26 RPOHFR_1 E27 RPOHFR_2 C28 RPOHFR_3 C29 RPOHCK_0 C30 RPOHCK_1 C31 ...
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... Intel IXF6048 — 51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface Table 4. Pin Description (Sheet 20 of 66) Pin Name Pin TPOH_0 N3 TPOH_1 N5 TPOH_2 M1 TPOH_3 L1 TPOHINS_0 M3 TPOHINS_1 M4 TPOHINS_2 N6 TPOHINS_3 K1 TPOHFR_0 N1 TPOHFR_1 P5 TPOHFR_2 P6 TPOHFR_3 N2 TPOHCK_0 P1 TPOHCK_1 P2 TPOHCK_2 P3 TPOHCK_3 P4 TPAL_0 L2 TPAL_1 M5 TPAL_2 L3 TPAL_3 J1 NOTE: See notes 1, 2, and ...
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... Mbit/s SONET/SDH Cell/Packet Interface — Intel IXF6048 Table 4. Pin Description (Sheet 21 of 66) Pin Name Pin RRD H30 RRDC L26 RMD F27 RMDC H26 TRD U2 TRDC Y4 TMD R4 TMDC V6 RROW G27 RMOW E31 RDOW J26 ROWBYC H31 ROWC J30 TROW R6 TMOW U1 NOTE: See notes 1, 2, and ...
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... Intel IXF6048 — 51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface Table 4. Pin Description (Sheet 22 of 66) Pin Name Pin TDOW T6 TOWBYC W4 TOWC W5 RPOW1 E29 RPOW2 F28 RPOWBYC K27 RPOWC J31 TPOW1 R5 TPOW2 T3 TPOWBYC AA1 TPOWC AA2 NOTE: See notes 1, 2, and 36 Type Transmit MSOH F1 Orderwire. TDOW is a 64-Kbit/s input for the LVTTL transmitted orderwire byte F1 ...
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... Mbit/s SONET/SDH Cell/Packet Interface — Intel IXF6048 Table 4. Pin Description (Sheet 23 of 66) Pin Name Pin OH and Alarm Insertion/Extraction Ports Quad PHY Mode (OH Ports Logical Interface #2) (Quad OC- RSOH_0 H29 RSOH_1 K26 RSOH_2 J28 RSOH_3 G31 RSOHFR_0 J29 RSOHFR_1 H30 RSOHFR_2 H31 ...
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... Intel IXF6048 — 51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface Table 4. Pin Description (Sheet 24 of 66) Pin Name Pin TSOHCK_0 AA3 TSOHCK_1 Y4 TSOHCK_2 W5 TSOHCK_3 AA2 TSAL_0 R3 TSAL_1 R4 TSAL_2 R6 TSAL_3 R5 TSALFR_0 T4 TSALFR_1 U2 TSALFR_2 U1 TSALFR_3 T3 TSALCK_0 V3 TSALCK_1 U3 TSALCK_2 T6 TSALCK_3 T5 RPOH_0 E26 RPOH_1 A29 RPOH_2 B28 RPOH_3 ...
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... Mbit/s SONET/SDH Cell/Packet Interface — Intel IXF6048 Table 4. Pin Description (Sheet 25 of 66) Pin Name Pin TPOH_0 N3 TPOH_1 N5 TPOH_2 M1 TPOH_3 L1 TPOHINS_0 M3 TPOHINS_1 M4 TPOHINS_2 N6 TPOHINS_3 K1 TPOHFR_0 N1 TPOHFR_1 P5 TPOHFR_2 P6 TPOHFR_3 N2 TPOHCK_0 P1 TPOHCK_1 P2 TPOHCK_2 P3 TPOHCK_3 P4 TPAL_0 L2 TPAL_1 M5 TPAL_2 L3 TPAL_3 J1 NOTE: See notes 1, 2, and ...
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... Intel IXF6048 — 51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface Table 4. Pin Description (Sheet 26 of 66) Pin Name Pin (OH Ports Logical Interface #3) (Quad OC-12c, OC-3c, and OC-1 modes) RRD_0 H29 RRD_1 K26 RRD_2 J28 RRD_3 G31 RRDC_0 K28 RRDC_1 L26 RRDC_2 J30 RRDC_3 J31 ...
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... Mbit/s SONET/SDH Cell/Packet Interface — Intel IXF6048 Table 4. Pin Description (Sheet 27 of 66) Pin Name Pin RDOW_0 E26 RDOW_1 A29 RDOW_2 B28 RDOW_3 D27 ROWBYC_0 F26 ROWBYC_1 E27 ROWBYC_2 C28 ROWBYC_3 C29 ROWC_0 C30 ROWC_1 C31 ROWC_2 D28 ROWC_3 D29 TROW_0 ...
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... Intel IXF6048 — 51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface Table 4. Pin Description (Sheet 28 of 66) Pin Name Pin TPOW1 M3 TPOW2 N3 TPOWBYC T4 TPOWC U2 NOTE: See notes 1, 2, and 42 Type Transmit POH F2 Orderwire. TPOW1 is a 64-Kbit/s input for the LVTTL transmitted orderwire byte F2. Input TPOW1 is synchronized with TPOWBYC and clocked in by TPOWC. ...
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... R_UICHCNF), a data transfer happens one (UTOPIA Level 2) or two (UTOPIA Level 3) clock cycles after the assertion of RXENB. NOTE: To operate in Level 3 mode (Intel IXF6048 does not share the interface with other PHYs) RcvMphyDevCnf must be set to logic zero. NOTE: If the receive interface operates in Level 2 or Level 1 modes and Intel IXF6048 does not share the interface with other PHYs, then RcvMphyDevCnf should be set to logic zero ...
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... In this configuration, the device uses only section overhead extraction. This configuration may be used in OC-12 and Quad OC- 12c modes. LVTTL Output 4 mA Receive UTOPIA Clock. This input clock provides timing for the Intel LVTTL IXF6048 receive system interface. RXCLK must cycle at a 104 MHz, or Input lower, instantaneous rate the end of the table ...
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... NOTE: See notes 1, 2, and Datasheet Type Receive Read Enable. RXENB is the active-low receive enable and controls read access from the Intel IXF6048 receive interface. RXENB can be used in two different ways: Normal Mode (with port selection phase) This is the default configuration (RcvSelMode = '0', register R_UICNF) compatible with the UTOPIA Level 3 and Level 2 specifications. • ...
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... Intel IXF6048 — 51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface Table 4. Pin Description (Sheet 32 of 66) Pin Name Pin RXPRTY D12 RXERR E13 NOTE: See notes 1, 2, and 46 Type Receive Data Parity. This output signal indicates the parity of RXDATA. Odd or even parity are selectable (see RcvPrtyCnf in register LVTTL R_UICHCNF) ...
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... Mbit/s SONET/SDH Cell/Packet Interface — Intel IXF6048 Table 4. Pin Description (Sheet 33 of 66) Pin Name Pin F13 RXVAL NOTE: See notes 1, 2, and Datasheet Type Receive Valid Data Output. RXVAL (active-high) validates the receive output signals RXDATA, RXSOF, RXEOF, RXERR, and RXPADL. Note that RXPRTY is valid independently of RXVAL. RXVAL is used only in POS mode ...
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... RXPADL[2:0] are held in high impedance. RXPADL[2:0] are driven or tristated following the same rules as RXDATA. Intel IXF6048 only outputs complete words on RXDATA except in the last word of a packet. RXPADL[2:0] should be used only when RXEOF is asserted (in the last word of a packet). When RXEOF is not asserted, RXPADL[2:0] outputs the value '000' indicating that all the bytes are valid ...
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... Mbit/s SONET/SDH Cell/Packet Interface — Intel IXF6048 Table 4. Pin Description (Sheet 35 of 66) Pin Name Pin RXPFA B9 NOTE: See notes 1, 2, and Datasheet Type Receive Polled Frame-Available Output. RXPFA (active-high tristatable signal used to indicate that the polled receive FIFO contains data. ...
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... Intel IXF6048 — 51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface Table 4. Pin Description (Sheet 36 of 66) Pin Name Pin RXFA_0 B12 RXFA_1 A17 RXFA_2 E20 RXFA_3 A26 NOTE: See notes 1, 2, and 50 Type Receive Direct Frame-Available Outputs. RXFA_i ( tristatable active-high signal used to indicate the status of receive FIFO #i ...
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... Mbit/s SONET/SDH Cell/Packet Interface — Intel IXF6048 Table 4. Pin Description (Sheet 37 of 66) Pin Name Pin Transmit Single MPHY ATM/POS-UTOPIA Interface (Level 3 and Level 2 Modes) TXDATA[0] K3 TXDATA[1] J3 TXDATA[2] L5 TXDATA[3] G1 TXDATA[4] L6 TXDATA[5] J4 TXDATA[6] H2 TXDATA[7] K6 TXDATA[8] G3 TXDATA[9] H5 TXDATA[10] F3 TXDATA[11] J6 TXDATA[12] E1 TXDATA[13] G4 TXDATA[14] F4 TXDATA[15] ...
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... In this configuration, the device uses only section overhead insertion. This configuration may be used in OC-12 and Quad OC- 12c modes. LVTTL Input Transmit UTOPIA Clock. TXCLK provides timing for the Intel IXF6048 LVTTL transmit UTOPIA interface. TXCLK must cycle at a 104 MHz, or lower, Input instantaneous rate. ...
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... Mbit/s SONET/SDH Cell/Packet Interface — Intel IXF6048 Table 4. Pin Description (Sheet 39 of 66) Pin Name Pin TXENB D9 TXADDR[0] A8 TXADDR[1] C9 TXADDR[2] D10 TXADDR[3] A9 TXADDR[4] D11 TXSOF M6 TXEOF H1 TXPRTY J2 NOTE: See notes 1, 2, and Datasheet Type Transmit Write Enable. TXENB (active-low) controls write access to the transmit interface ...
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... TXPADL[2:0] are unused inputs. Intel IXF6048 only accepts complete words on TXDATA except in the last word of a packet. Intel IXF6048 uses TXPADL[2:0] only when TXEOF is asserted (in the last word of a packet). When configured in 64-bit mode, the last word may contain zero, one, two, three, four, five, six, or seven padding bytes ...
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... Mbit/s SONET/SDH Cell/Packet Interface — Intel IXF6048 Table 4. Pin Description (Sheet 41 of 66) Pin Name Pin TXPFA B6 TXSFA C5 NOTE: See notes 1, 2, and Datasheet Type Transmit Polled Frame-Available Output. TXPFA (active-high tristatable signal used to indicate that the polled transmit FIFO has free available space ...
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... Intel IXF6048 — 51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface Table 4. Pin Description (Sheet 42 of 66) Pin Name Pin TXFA_0 D8 TXFA_1 A5 TXFA_2 A6 TXFA_3 E8 NOTE: See notes 1, 2, and 56 Type Transmit Direct Frame-Available Outputs. TXFA_i ( tristatable active-high signal used to indicate the status of transmit FIFO #i. XmtDirStatCnf (global register T_UICNF) uses the TXFA_i outputs in two different ways: • ...
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... Level 1) or two (UTOPIA Level 3) clock cycles after the assertion of RXENB_i ( 3). RXDATA_i[7:0] are updated on the rising edge of RXCLK_i ( 3). Receive UTOPIA Clock. RXCLK_i ( provides timing for the LVTTL Intel IXF6048 receive system interface #i. RXCLK_i ( must Input cycle at a 104 MHz, or lower, instantaneous rate the end of the table. Description ...
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... Intel IXF6048 — 51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface Table 4. Pin Description (Sheet 44 of 66) Pin Name Pin RXENB_0 E19 RXENB_1 D19 RXENB_2 F19 RXENB_3 C20 RXSOF_0 B11 RXSOF_1 C14 RXSOF_2 A22 RXSOF_3 B25 RXEOF_0 C12 RXEOF_1 D15 RXEOF_2 B21 RXEOF_3 A25 RXPRTY_0 ...
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... Mbit/s SONET/SDH Cell/Packet Interface — Intel IXF6048 Table 4. Pin Description (Sheet 45 of 66) Pin Name Pin RXVAL_0 F13 RXVAL_1 E15 RXVAL_2 A23 RXVAL_3 D24 NOTE: See notes 1, 2, and Datasheet Type Receive Valid Data Output. RXVAL_i ( the active-high data validation signal. RXVAL_i validates the receive output signals for interface #i: RXDATA_i, RXSOF_i, RXEOF_i, and RXERR_i ...
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... Intel IXF6048 — 51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface Table 4. Pin Description (Sheet 46 of 66) Pin Name Pin RXFA_0 B12 RXFA_1 A17 RXFA_2 E20 RXFA_3 A26 NOTE: See notes 1, 2, and 60 Type Receive Direct Frame-Available Output. RXFA_i ( the active-high output signal indicating the status of receive FIFO #i. ...
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... FIFO #i only when TXENB_i is asserted. Input TXDATA_i[7: sampled on the rising edge of TXCLK_i. Transmit UTOPIA Clock. TXCLK_i ( provides timing for the LVTTL Intel IXF6048 transmit UTOPIA interface. TXCLK_i must cycle at a 104 Input MHz, or lower, instantaneous rate the end of the table. ...
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... Intel IXF6048 — 51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface Table 4. Pin Description (Sheet 48 of 66) Pin Name Pin TXENB_0 D9 TXENB_1 F9 TXENB_2 B8 TXENB_3 E9 TXSOF_0 M6 TXSOF_1 K5 TXSOF_2 H6 TXSOF_3 C2 TXEOF_0 H1 TXEOF_1 G2 TXEOF_2 G5 TXEOF_3 F6 TXPRTY_0 J2 TXPRTY_1 H4 TXPRTY_2 D1 TXPRTY_3 E6 TXERR_0 K4 TXERR_1 J5 TXERR_2 E3 TXERR_3 C4 NOTE: See notes 1, 2, and ...
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... Mbit/s SONET/SDH Cell/Packet Interface — Intel IXF6048 Table 4. Pin Description (Sheet 49 of 66) Pin Name Pin TXFA_0 D8 TXFA_1 A5 TXFA_2 A6 TXFA_3 E8 NOTE: See notes 1, 2, and Datasheet Type Transmit Direct Frame-Available Outputs. TXFA_i ( the active-high output signal indicating the status of transmit FIFO #i. ...
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... Intel IXF6048 — 51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface Table 4. Pin Description (Sheet 50 of 66) Pin Name Pin Receive Quad 16-Bit Mode ATM/POS-UTOPIA Interface (Level 3 and Level 1 Modes) RXDATA_0[0] D13 RXDATA_0[1] B13 RXDATA_0[2] A12 RXDATA_0[3] A14 RXDATA_0[4] A13 RXDATA_0[5] D14 RXDATA_0[6] F14 RXDATA_0[7] ...
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... LVTTL Output 4 mA Receive UTOPIA Clock. RXCLK_i ( provides timing for the LVTTL Intel IXF6048 receive system interface #i. RXCLK_i ( must Input cycle MHz or lower instantaneous rate. Receive Read Enable. RXENB_i ( the active-low receive enable that controls read access from receive interface #i. • When RXENB_i ( deasserted, nothing happens on interface #i ...
Page 66
... Intel IXF6048 — 51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface Table 4. Pin Description (Sheet 52 of 66) Pin Name Pin RXSOF_0 B11 RXSOF_1 C14 RXSOF_2 A22 RXSOF_3 B25 RXEOF_0 C12 RXEOF_1 D15 RXEOF_2 B21 RXEOF_3 A25 RXPRTY_0 D12 RXPRTY_1 C15 RXPRTY_2 B22 RXPRTY_3 D23 RXERR_0 ...
Page 67
... RXDATA_i[15:0]. RXPADL_i is used only in POS mode; in ATM mode, RXPADL_i is held in high impedance. Intel IXF6048 only outputs complete words on RXDATA_i ( except in the last word of a packet. RXPADL_i should be used only when RXEOF_i is asserted (in the last word of a packet); when RXEOF_i is not ...
Page 68
... Intel IXF6048 — 51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface Table 4. Pin Description (Sheet 54 of 66) Pin Name Pin RXFA_0 B12 RXFA_1 A17 RXFA_2 E20 RXFA_3 A26 NOTE: See notes 1, 2, and 68 Type Receive Direct Frame-Available Output. RXFA_i ( the active-high output signal indicating the status of receive FIFO #i. ...
Page 69
... Mbit/s SONET/SDH Cell/Packet Interface — Intel IXF6048 Table 4. Pin Description (Sheet 55 of 66) Pin Name Pin Transmit Quad 16-Bit Mode ATM/POS-UTOPIA Interface (Level 3 and Level 1 Modes) TXDATA_0[0] K3 TXDATA_0[1] J3 TXDATA_0[2] L5 TXDATA_0[3] G1 TXDATA_0[4] L6 TXDATA_0[5] J4 TXDATA_0[6] H2 TXDATA_0[7] K6 TXDATA_0[8] G3 TXDATA_0[9] H5 TXDATA_0[10] F3 TXDATA_0[11] J6 TXDATA_0[12] E1 TXDATA_0[13] G4 TXDATA_0[14] ...
Page 70
... This configuration could be used in Quad OC-12c mode. LVTTL Input Transmit UTOPIA Clock. TXCLK_i ( provides timing for the LVTTL Intel IXF6048 transmit UTOPIA interface. TXCLK_i must cycle Input MHz or lower instantaneous rate. Transmit Write Enable. TXENB_i ( the active-low transmit enable that controls write access to transmit interface #i. ...
Page 71
... TXDATA_i[15:0]. TXPADL_i is used only in POS mode; in ATM-UTOPIA mode TXPADL_i ( are unused inputs. Intel IXF6048 only accepts complete words on TXDATA_i[15:0] except in the last word of a packet. Intel IXF6048 uses TXPADL_i only when TXEOF_i ( asserted (in the last word of a packet). LVTTL When configured in 16-bit mode, the last word may contain zero or one Input padding byte ...
Page 72
... Intel IXF6048 — 51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface Table 4. Pin Description (Sheet 58 of 66) Pin Name Pin TXFA_0 D8 TXFA_1 A5 TXFA_2 A6 TXFA_3 E8 NOTE: See notes 1, 2, and 72 Type Transmit Direct Frame-Available Outputs. TXFA_i ( the active-high output signal indicating the status of transmit FIFO #i. TXFA_i ( outputs are always driven. ...
Page 73
... Write-Bar Intel; Read/Write Bar Motorola* Input LVTTL Read-Bar Intel; Enable Motorola* Input Interrupt Request. INT goes low when an Intel IXF6048 interrupt bit is LVTTL active and unmasked. After clearing the interrupt bit (by reading the Output corresponding register), INT goes to high impedance. INT is an open drain output that requires an external pull-up resistor ...
Page 74
... Intel IXF6048 — 51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface Table 4. Pin Description (Sheet 60 of 66) Pin Name Pin GENIO K31 RESET N30 OEN N31 UOEN P27 NOTE: See notes 1, 2, and 74 Type Generic Input/output Controllable Via the Microprocessor Interface If configuration bit GenIOMode (register GOCNF) is set to ‘0’, then GENIO ball is an input ...
Page 75
... Mbit/s SONET/SDH Cell/Packet Interface — Intel IXF6048 Table 4. Pin Description (Sheet 61 of 66) Pin Name Pin JTCK L28 JTMS M26 JTRS L29 JTDI L30 JTDO L27 SCANTEST M29 SCANEN M30 NOTE: See notes 1, 2, and Datasheet Type JTAG and SCAN Test Ports LVTTL JTAG Clock ...
Page 76
... Intel IXF6048 — 51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface Table 4. Pin Description (Sheet 62 of 66) Pin Name Pin VDD_CORE A11 VDD_CORE C6 VDD_CORE AA6 VDD_CORE AB29 VDD_CORE AG4 VDD_CORE AG22 VDD_CORE AH9 VDD_CORE AH30 VDD_CORE AJ11 VDD_CORE AL16 VDD_CORE AL18 VDD_CORE C3 VDD_CORE D31 VDD_CORE ...
Page 77
... Mbit/s SONET/SDH Cell/Packet Interface — Intel IXF6048 Table 4. Pin Description (Sheet 63 of 66) Pin Name Pin GND_CORE AA28 GND_CORE AD3 GND_CORE AF28 GND_CORE AG9 GND_CORE AH2 GND_CORE AH22 GND_CORE AJ17 GND_CORE AL11 GND_CORE AL15 GND_CORE C11 GND_CORE B29 GND_CORE B5 GND_CORE C17 ...
Page 78
... Intel IXF6048 — 51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface Table 4. Pin Description (Sheet 64 of 66) Pin Name Pin VDD_TTL A24 VDD_TTL AA4 VDD_TTL AC6 VDD_TTL AD2 VDD_TTL AD28 VDD_TTL AE3 VDD_TTL AF7 VDD_TTL AF9 VDD_TTL AG7 VDD_TTL AG26 VDD_TTL AH6 VDD_TTL AH26 VDD_TTL ...
Page 79
... Mbit/s SONET/SDH Cell/Packet Interface — Intel IXF6048 Table 4. Pin Description (Sheet 65 of 66) Pin Name Pin GND_TTL A1 GND_TTL A2 GND_TTL A15 GND_TTL A16 GND_TTL A30 GND_TTL A31 GND_TTL AK1 GND_TTL AK2 GND_TTL AK3 GND_TTL AK4 GND_TTL AK28 GND_TTL AK29 GND_TTL AK30 GND_TTL ...
Page 80
... Intel IXF6048 — 51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface Table 4. Pin Description (Sheet 66 of 66) Pin Name Pin VDD_PECL AJ26 VDD_PECL AJ22 VDD_PECL AL19 VDD_PECL AH17 VDD_PECL AJ16 VDD_PECL AH14 VDD_PECL AH15 VDD_PECL AH12 VDD_PECL AH13 VDD_PECL AF10 VDD_PECL AF11 VDD_PECL AJ7 VDD_PECL ...
Page 81
... Mbit/s SONET/SDH Cell/Packet Interface — Intel IXF6048 Table 5. PECL I/O Pin Equivalence on the Line Side Interface Pin # AH20 AJ20 AF20 AG20 AK21 AL21 AH21 AJ21 AF21 AG21 AK22 AL22 AK23 AL23 AH23 AJ23 AF23 AG23 AK24 AL24 AH24 RPDI_P[10] AJ24 ...
Page 82
... Intel IXF6048 — 51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface Table 6. I/O Pin Equivalence on the Receive TTL Line Side Interface (Sheet TTL Pin # Parallel Single W26 RPDI[0] W27 RPDI[1] AA30 RPDI[2] AA31 RPDI[3] Y29 RPDI[4] AB31 RPDI[5] Y28 RPDI[6] AA29 RPDI[7] AA26 RPDI[8] ...
Page 83
... Mbit/s SONET/SDH Cell/Packet Interface — Intel IXF6048 Table 6. I/O Pin Equivalence on the Receive TTL Line Side Interface (Sheet TTL Pin # Parallel Single AA27 ROOF AB30 RFPI AB26 AC28 AE31 AE29 AE30 AG30 AE27 AH31 AG29 AD26 AF26 AH27 AJ28 AJ27 ...
Page 84
... Intel IXF6048 — 51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface Table 7. I/O Pin Equivalence on the Transmit TTL Line Side Interface Tx TTL Pin # Parallel Single AF6 TPDO[0] AJ4 TPDO[1] AH4 TPDO[2] AG5 TPDO[3] AE6 TPDO[4] AJ2 TPDO[5] AF5 TPDO[6] AJ1 TPDO[7] AE5 TPDO[8] AF4 ...
Page 85
... Mbit/s SONET/SDH Cell/Packet Interface — Intel IXF6048 Table 8. TTL I/O Pin Equivalence on the Receive OH/Alarm Extraction Ports (Sheet Extraction Pin # Logical Interface #1 H29 RSOH_0 J29 RSOHFR K28 RSOHCK E28 RSAL E30 RSALFR H27 RSALCK E26 RPOH_0 F26 RPOHFR_0 C30 RPOHCK_0 ...
Page 86
... Intel IXF6048 — 51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface Table 8. TTL I/O Pin Equivalence on the Receive OH/Alarm Extraction Ports (Sheet Extraction Pin # Logical Interface #1 F30 H28 J27 86 OH Extraction OH Extraction Logical Logical Interface #2 Interface #3 Rx UTOPIA Rx UTOPIA Single 64-bit Quad 16-bit RXDATA[61] ...
Page 87
... Mbit/s SONET/SDH Cell/Packet Interface — Intel IXF6048 Table 9. TTL I/O Pin Equivalence on the Transmit OH/Alarm Insertion Ports (Sheet Insertion Pin # Logical Interface #1 W2 TSOHINS_0 W3 TSOH_0 Y3 TSOHFR AA3 TSOHCK R3 TSAL T4 TSALFR V3 TSALCK M3 TPOHINS_0 N3 TPOH_0 N1 TPOHFR_0 P1 TPOHCK_0 L2 TPAL_0 U6 TSOHINS_1 Y2 TSOH_1 V6 TMDC Y4 TRDC ...
Page 88
... Intel IXF6048 — 51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface Table 9. TTL I/O Pin Equivalence on the Transmit OH/Alarm Insertion Ports (Sheet Insertion Pin # Logical Interface #1 L3 TPAL_2 W1 TSOHINS_3 Y1 TSOH_3 AA1 TPOWBYC AA2 TPOWC R5 TPOW1 T3 TPOW2 T5 K1 TPOHINS_3 L1 TPOH_3 N2 TPOHFR_3 P4 TPOHCK_3 J1 TPAL_3 88 OH Insertion ...
Page 89
... Mbit/s SONET/SDH Cell/Packet Interface — Intel IXF6048 Table 10. TTL I/O Pin Equivalence on the Receive UTOPIA Interface (Sheet UTOPIA Pin # Single D13 RXDATA[0] B13 RXDATA[1] A12 RXDATA[2] A14 RXDATA[3] A13 RXDATA[4] D14 RXDATA[5] F14 RXDATA[6] B14 RXDATA[7] D16 RXDATA[8] B18 RXDATA[9] ...
Page 90
... Intel IXF6048 — 51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface Table 10. TTL I/O Pin Equivalence on the Receive UTOPIA Interface (Sheet UTOPIA Pin # Single E17 RXCLK E19 RXENB B11 RXSOF C12 RXEOF D12 RXPRTY E13 RXERR B12 RXFA_0 F13 RXVAL F17 D19 C14 D15 ...
Page 91
... Mbit/s SONET/SDH Cell/Packet Interface — Intel IXF6048 Table 11. TTL I/O Pin Equivalence on the Transmit UTOPIA Interface (Sheet UTOPIA Pin # Single K3 TXDATA[0] J3 TXDATA[1] L5 TXDATA[2] G1 TXDATA[3] L6 TXDATA[4] J4 TXDATA[5] H2 TXDATA[6] K6 TXDATA[7] G3 TXDATA[8] H5 TXDATA[9] F3 TXDATA[10] J6 TXDATA[11] E1 TXDATA[12] G4 TXDATA[13] F4 TXDATA[14] E2 TXDATA[15] D3 TXDATA[16] D2 TXDATA[17] F5 TXDATA[18] E4 TXDATA[19] ...
Page 92
... Intel IXF6048 — 51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface Table 11. TTL I/O Pin Equivalence on the Transmit UTOPIA Interface (Sheet UTOPIA Pin # Single D11 TXADDR[4] A7 TXPADL[0] C7 TXPADL[1] C8 TXPADL[ TXPFA C5 TXSFA F10 TXCLK D9 TXENB M6 TXSOF H1 TXEOF J2 TXPRTY K4 TXERR D8 TXFA_0 E10 TXFA_1 F11 TXFA_2 E11 ...
Page 93
... Mbit/s SONET/SDH Cell/Packet Interface — Intel IXF6048 2.0 Main Features 2.1 General • Intel IXF6048 maps/demaps both ATM cells or byte-synchronous HDLC frames (packet over SONET mode) over SONET/SDH. • The device processes the following SONET/SDH frame formats: — Single STS-48c/STM-16c — Single STS-48/STM-16 — ...
Page 94
... Intel IXF6048 — 51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface • K1, K2 (APS), S1 (synchronization message status), and C2 (path Signal Label) received bytes filtering; parallel access (via microprocessor) and serial access (via Receive Section serial Alarm bus: RSAL output). • Full J0 and J1 (Trace Identifiers) processing programmable as a 1-, 16- (with CRC-7), or 64- byte trace ...
Page 95
... Mbit/s SONET/SDH Cell/Packet Interface — Intel IXF6048 • Insertion of DCC channels (D1-D3 D12) and orderwire channels (E1, E2, F1) either from the dedicated serial ports (at 192-, 576- and 64-Kbit/s) or from the Transmit Section serial OverHead bus (TSOH). • Calculation (after scrambling) and insertion of multiplexer section BIP-8/24/96/392 (B2 bytes) and regenerator section BIP-8 (B1). • ...
Page 96
... Intel IXF6048 — 51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface • The number of cells containing a correctable error in the header are counted in a 16-bit counter. • The number of cells containing an uncorrectable error in the header are counted in a 16-bit counter. • The number of accepted cells that have been lost due to a FIFO overflow are counted in a 16- bit counter ...
Page 97
... The number of bytes received and written into the receive FIFO are counted in an 32-bit counter. Intel IXF6048 can be configured to count all the bytes written into the FIFO (good frames + frames marked as errored) or only the bytes received within good frames. • ...
Page 98
... Intel IXF6048 — 51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface — UTOPIA Level 3 with four independent 16-bit data buses — UTOPIA Level 3 with four independent 8-bit data buses — UTOPIA Level 2 with 16-bit data bus — UTOPIA Level 2 with 8-bit data bus — UTOPIA Level 1 (four independent interfaces) • ...
Page 99
... Mbit/s SONET/SDH Cell/Packet Interface — Intel IXF6048 2.1.8 POS-UTOPIA Interface • POS-UTOPIA interface, based on the ATM industry standard UTOPIA and supporting the transfer of variable length packets: — POS-UTOPIA Level 3 with 64-bit data bus — POS-UTOPIA Level 3 with 32-bit data bus — ...
Page 100
... However, in order to use the Line Loopback mode or to clock a transmit channel with the corresponding receive channel timing reference necessary to configure the receive and transmit line side interfaces in the same mode. These are the main configuration features of Intel IXF6048 line side interface: • ...
Page 101
... Figure 3 shows an example of an Intel IXF6048 connected to a 2488 Mbit/s Mux/Demux PECL chipset. Optionally, Intel IXF6048 can be controlled by an external frame acquisition block by using the input RFPI_P/N (receive frame position input). The parallel transmit interface can also be controlled by an external 8-KHz system reference by using the input TFPI_P/N. That allows the use of four Intel IXF6048 devices to build an OC-48/OC-192 Multiplexer/Demultiplexer ...
Page 102
... Mbit Mbit/s. Each transmit channel has been configured to use an independent input timing reference (TSCI_Pi/Ni 3). The serial line side interface can also be used when Intel IXF6048 is configured as a single STS-3 (non concatenated) processor. In this configuration, only one serial line side interface (channel 0) is active ...
Page 103
... RPDI_i[7:0] and TPDO_i[7: 3). Each TTL parallel receive interface does not require external frame acquisition circuitry, i.e., the input on each data bus RPDI_i[7: not required to carry byte-aligned SONET/SDH data; Intel IXF6048 performs internal (on-chip) frame acquisition and word rotation on each data stream. Optionally, each Intel IXF6048 receive interface can be controlled by an external frame acquisition block by using the input RFPI_i (receive frame position input) ...
Page 104
... Intel IXF6048 — 51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface The TTL 8-bit parallel line side interface can also be used when Intel IXF6048 is configured as a single STS-12 (non concatenated) processor. In this configuration, only one TTL parallel line side interface (channel 0) is active. 3.5 ...
Page 105
... The transmit source of the RSOH bytes is configurable via a microprocessor register. timing is recovered by the high-speed line interface unit and passed to the transmit side via the Intel IXF6048. In the event of a receiver failure (i.e., a LOS of Signal Alarm), the Intel IXF6048 switches to the selected transmit line (Blue) clock signal reference (if so configured— ...
Page 106
... Intel IXF6048 — 51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface Figure 6. OC-48 Repeater Application INTERFACE REPEATER Application Single 2.5 Gbps configuration OC-48 Line Side 2.5 Gbit/s 16 bits parallel Receiver data+Clock OPT (OC-48 CDR) Rx 155.52 MHz +/- 20 ppm Local Reference (selected transmit line) for the "Blue" ...
Page 107
... M1 is sourced from the TSOH input, the Transmit Section Alarm serial bus input (TSAL internal process that sets M1 based on the receive B2 byte(s) errors from the receive portion of the Intel IXF6048 if automatic MS-REI insertion is enabled. • E2 may be sourced from the TMOW dedicated serial port configured, or the TSOH serial input ...
Page 108
... Intel IXF6048 — 51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface TOWC and an 8-KHz sync pulse at TOWBYC. In repeater mode, this byte can also be passed through unchanged. • F1 may be sourced from the TDOW dedicated serial input configured, or the TSOH serial bus input. In the case of a dedicated serial port, a 64-KHz reference clock is supplied at TOWC and an 8-KHz sync pulse at TOWBYC ...
Page 109
... Mbit/s SONET/SDH Cell/Packet Interface — Intel IXF6048 • provided serially either at the RROW dedicated output or at the serial output bus RSOH. • provided serially at the RDOW dedicated output or at the RSOH output bus. In the case of a dedicated serial ports, E1 and F1 are synchronous and can be accessed using the 64-KHz clock provided at RROWC and the 8-KHz synchronization pulse provided at ROWBYC. • ...
Page 110
... Receiver Default Operation Per Channel Figure block diagram of the receive section of one SONET/SDH block of the Intel IXF6048. The detailed description below follows the data flow from left to right, describing the functionality and configuration of each SONET/SDH receive framer block. Note that all status change alarms, counter overflow alarms, and receive byte change alarms mentioned, can cause the INT output pin to be activated if they are unmasked ...
Page 111
... For single OC-48 channel operation, the input data may be parallel with 16-bit wide bus input at RPDI_P/N[15: 32-bit wide bus input at RPDI[31:0]. No specific order on the 8-bit, 16-bit, or 32-bit is required for the Intel IXF6048 to operate. The parallel clock is input at RPCI or RPCI_P/N, and the serial clock at RSCI_P/N. ...
Page 112
... Intel IXF6048 — 51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface 4.4.1.2 Framer The framer operates on a serial (OC-1/3), parallel 8-bit wide (OC-1/3/12), or parallel 8/16/32-bit wide (OC-48) data input stream. It does not require any external framing in the Line Interface chip as the 8/16/32-bit data input does not have to be aligned in the byte boundary example, when using a 16-bit wide parallel interface at OC-48, the framer eliminates the sixteen phases (bits) of ambiguity and memorizes the position of the framing word ...
Page 113
... Mbit/s SONET/SDH Cell/Packet Interface — Intel IXF6048 Figure 8. Framing State Machine In Frame Desynchronization cycle is from In Frame State to Out Of Frame State. Acquisition cycle is from Out Of frame State to In Frame State. OOF Alarm is disabled and receive demultiplexer is re-synchronized, according to the new frame boundary, when entering into the In Frame State. ...
Page 114
... Intel IXF6048 — 51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface Figure 9. STS-1/STM-0 Robust Framing State Machine Desynchronization cycle is from Locked In Frame State to Out Of Frame State. Acquisition cycle is from Out Of frame State to In Frame State. Transition cycle is from In Frame State to Locked In Frame State. OOF Alarm is disabled and receive demultiplexer is re-synchronized, according to the new frame boundary, when entering in the In Frame State ...
Page 115
... Mbit/s SONET/SDH Cell/Packet Interface — Intel IXF6048 Out Of Frame conditions required to enter a Loss Of Frame state—this value is the LOF_LMN register bits[14:10] setting plus 1 (in other words bits[14:10] + 1). The value always 1 through 32. Status changes in the OOF and LOF detectors generate OOF and LOF alarms. Also, output from these detectors is provided at the OOF and LOF output pins ...
Page 116
... Intel IXF6048 — 51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface Figure 11. Overhead Bytes for the OC-n Section OverHead (SOH) bytes for OC-n : 24xn bytes (RSOH & MSOH RSOH rows D4 D7 MSOH D10 S1 NU 4.4.1.3.1 The Regenerator Section Trace J0 This byte is used to repetitively transmit a Section Access Identifier so that a section receiver can verify its continued connection to the intended transmitter ...
Page 117
... Mbit/s SONET/SDH Cell/Packet Interface — Intel IXF6048 For a 16-byte trace message, the receiver calculates the CRC-7 of the received J0 string. In the case transmission error in the J0 string string CRC-7 error (J0Crc7Err) is indicated in register IS_RG specific byte of the received J0 trace is not equal to its expected value for 3 consecutive received traces (64 × ...
Page 118
... Intel IXF6048 — 51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface 4.4.1.3.6 National Used/Z0 Bytes, Media Dependent, and Undefined Bytes of the RSOH These bytes are only relevant in OC-3/12/48 mode and can only be accessed via the serial RSOH output. 4.4.1.3.7 Receive Regenerator Section AIS (RstAIS) The AIS generated after the Regenerator Section is labeled RstAis ...
Page 119
... Mbit/s SONET/SDH Cell/Packet Interface — Intel IXF6048 . Table 12. EED Register Settings 3 ExcB2Min - V Set 4 ExcB2Max - V ExcB2SetWinSz ExcB2ClrWinSz ExcB2SetWinNum ExcB2ClrWinNum 3 ExcB2Min - V Set 4 ExcB2Max - V ExcB2SetWinSz ExcB2ClrWinSz ExcB2SetWinNum ExcB2ClrWinNum 3 ExcB2Min - V Set 4 ExcB2Max - V ExcB2SetWinSz ExcB2ClrWinSz ExcB2SetWinNum ExcB2ClrWinNum 3 ExcB2Min - V Set 4 ExcB2Max - V ExcB2SetWinSz ExcB2ClrWinSz ExcB2SetWinNum ExcB2ClrWinNum NOTES: 1 ...
Page 120
... Intel IXF6048 — 51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface Table 13. DSD Registers Setting BER 3 DegB2Min - V Set 4 DegB2Max - V DegB2SetWinSz DegB2ClrWinSz DegB2SetWinNum DegB2ClrWinNum 3 DegB2Min - V Set 4 DegB2Max - V DegB2SetWinSz DegB2ClrWinSz DegB2SetWinNum DegB2ClrWinNum 3 DegB2Min - V Set 4 DegB2Max - V DegB2SetWinSz DegB2ClrWinSz DegB2SetWinNum DegB2ClrWinNum 3 DegB2Min - V Set 4 DegB2Max - V DegB2SetWinSz DegB2ClrWinSz DegB2SetWinNum DegB2ClrWinNum NOTES: 1 ...
Page 121
... Where V is the number-of-B2-errors register field value for setting or clearing the window- size-component register field value for setting or clearing and is used to derive the number of frames in a window; and N is the STS line rate. See the Intel Calculation (EED/DSD) Application Note (order number 273717) for more details on BER threshold setting ...
Page 122
... Intel IXF6048 — 51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface 4.4.1.4.5 MS-REI Via M1 Byte This byte is allocated for the Remote Error Indication. Remote BIP errors are accumulated in a 21- bit counter, accessible via registers MR_BIPCNT. Remote block errors are accumulated in an 17- bit counter, accessible via registers MR_BLKCNT. ...
Page 123
... Mbit/s SONET/SDH Cell/Packet Interface — Intel IXF6048 4.4.1.4.10 Receive Multiplexer Section AIS (MS-AIS) The AIS generated after the multiplexer section is labeled MstAis. It can be inserted on the following conditions: • MS-AIS detection in K2 • EED detection The AIS insertion can disabled or forced via register R_MST_C. The EED dependency can be disabled via register R_MST_C (ITU specification) ...
Page 124
... Intel IXF6048 — 51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface • AU-AIS detection (all '1's. pointer for three consecutive frames and, if configured as such, all '1's. in the concatenation indicator bytes) • LOP detection • LOPC detection (the Loss Of Pointer Concatenation indication action on DmsaAis may be disabled/enabled via configuration register R_MSA_C) ...
Page 125
... Mbit/s SONET/SDH Cell/Packet Interface — Intel IXF6048 406/7 specification says to ignore mismatch and unstable alarms when there are phase changes in the incoming signal. The Trace Identifier Mismatch is also provided at the RPAL serial alarm bus output and the J1 received byte is serially accessible at RPOH bus output pin. ...
Page 126
... Intel IXF6048 — 51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface • C2 equal to all '0's (Unequipped) • First byte of the J1 accepted trace is equal to all '0's • J1 trace correct or incorrect (J1 Mismatch/Unstable) • B3 detected BIP/Block errors (B3 error counter) In addition, for the support of “supervisory unequipped” possible to disable HP-RDI generation and/or AIS generation because of the Unequipped (C2 = all '0's) detection, via configuration register R_HPT_C2 ...
Page 127
... Mbit/s SONET/SDH Cell/Packet Interface — Intel IXF6048 The receive F3 byte may be also serially accessible at RPOH bus output pin. 4.4.1.6.8 K3/Z4, H4, and N1/Z5 Bytes (Unused) These three bytes can only be accessed via the serial RPOH output bus pin. 4.4.1.6.9 Receive Higher Order Path AIS (HptAIS) The AIS generated after the HPOH receiver is labeled HptAis ...
Page 128
... Intel IXF6048 — 51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface Figure 12. SONET/SDH Transmitter Blocks Serial Orderwire Transmit POH Serial and alarm Interface Interface (Optional) (Optional) MCEN Higher order Path Transmitter MDATA[31..0] VC-4(c) / VC-3(c) (From the Transmit ATM Formatter) REI/RDI PATH FEBE 4.4.2.1.1 J1 Byte: Path Trace Identifier This byte is used to transmit a repetitive Path Trace Identifier so that a path receiver can verify its continued connection to the intended transmitter ...
Page 129
... Mbit/s SONET/SDH Cell/Packet Interface — Intel IXF6048 • The serial TPOH interface (TPOH input pin). • The incoming byte from the downstream data—when all POH bytes are configured in pass- through mode. • The BIP-8 calculation on the previous concatenated payload (default setting). For testing purposes possible to invert the B3 value via software configuration (see register T_HPT_OPC) ...
Page 130
... Intel IXF6048 — 51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface When internally supplied by the receiver, the HP-RDI bit generation and coding is configurable via register R_HPT_C1. Intel IXF6048 supports both enhanced or not enhanced HP-RDI (configurable via register T_HPT_OPC). The following defects in the receiver may generate an HP-RDI: — ...
Page 131
... Mbit/s SONET/SDH Cell/Packet Interface — Intel IXF6048 4.4.2.1.7 F2 Byte: Order Wire Channel (Optional) The F2 source is specified by register T_SC_RSOH, combined with input control pin TPOHINS, as coming from: • The 64-Kbit/s dedicated serial TPOW1 input port. • The serial TPOH interface (TPOH input pin). ...
Page 132
... For testing purposes, positive or negative pointer movements, as well as NDF indication (NDF transmit bits are set to '1001'), may be generated via the microprocessor (see AU pointer operational configuration register T_AU_PTS). The Intel IXF6048 only allows the generation of consecutive pointer movements separated by at least 4 frames. ...
Page 133
... Mbit/s SONET/SDH Cell/Packet Interface — Intel IXF6048 — An internal register (register MP_TK2K1) programmed by the microprocessor (default setting). The K2-APS source is specified by register T_SC_MSOH, combined with input serial bus control pin TSOHINS, as coming from: — The serial TSOH interface (TSOH input pin). ...
Page 134
... Intel IXF6048 — 51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface — The serial TSOH interface (TSOH input pin). — The incoming byte from the downstream data—when all internally Processed MSOH (B2, K1, K2, S1 and M1) bytes are configured in pass-through mode. — An internal register (MP_TS1) programmed by the microprocessor (default setting). ...
Page 135
... RSOH byte (except A1, A2, and B1) can group or passed through individually, unchanged. 4.4.2.4.1 A1 and A2 Framing Bytes The frame keyword bytes are always regenerated in the Intel IXF6048 transmitter regardless of the configuration. For testing purposes possible to invert A1 value (via register T_RMST_OP). The A1 value can be inverted for four frames only (to generate an OOF alarm for 2 frames in the receiver) or for an indefinite duration ...
Page 136
... Intel IXF6048 — 51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface 4.4.2.4.3 B1 BIP-8 Byte The B1 byte is always regenerated in the Intel IXF6048 transmitter. This byte is used for the Regenerator Section error monitoring function the result of a BIP-8 calculation done on the previously scrambled frame and is inserted into transmit RSOH before scrambling. For testing purpose possible to invert the B1 value (register T_RMST_OP) ...
Page 137
... Mbit/s SONET/SDH Cell/Packet Interface — Intel IXF6048 — The internal common unused Overhead byte transmit default value (all '0's). — The “Quiet” default value for orderwire channel dedicated to voice communication. This default value is '01111111'. 4.4.2.4.7 F1 Byte: Orderwire Channel (Optional) This byte is reserved for user purposes ...
Page 138
... TFPI input pin (except in repeater mode, in which case locked to the received frame). This input signal is active-high and can be either a square wave or a pulse. This feature can be used by an Upper Level Multiplexer (OC-192) to align several Intel IXF6048 chips. The alignment can be done by cascading the reference signals (output pin TFPO of chip #2 connected to input pin TFPI of chip #3, etc ...
Page 139
... TSOHINS input insert control pin is high at the MSB location of a specific SOH byte in the TSOH bus, this value is inserted into the transmit frame and output from the Intel IXF6048 one SDH row after it is latched. If the TSOHINS input control pin is low at the MSB location of a specific SOH ...
Page 140
... The transmit side of the POH serial interface allows insertion of each POH byte, or some bit of a byte, into the transmit HPOH via a serial contradirectional interface can process four independent paths, Intel IXF6048 provides up to four TPOH interfaces (one per channel or concatenated higher order VCs). ...
Page 141
... TPOHINS input insert control pin is high at any bit location of a specific POH byte in the TSOH input bus, this bit value is inserted into the transmit POH byte and output from the Intel IXF6048. If the TPOHINS input control pin is low at the bit location of a specific POH byte in the TPOH ...
Page 142
... K1 and K2 APS bytes, and the filtered S1 SSM via a serial codirectional interface can process four independent sections (four channels), Intel IXF6048 provides up to four RSAL interfaces (one per channel). For each channel, RSAL[i] provides the following detected alarms and information: — ...
Page 143
... K1 and K2 APS—see register R_MST_C). RSAL[i] may be configured as a ring port by connecting directly to the transmit alarm port (TSAL input) of another Intel IXF6048 chip. The Line RDI (MS-RDI) and line REI (MS-REI) information is now externally fed back. Therefore, the internal chip feedback of the remote defects is disabled. ...
Page 144
... Intel IXF6048 — 51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface — The data is output on the RSAL[i] pin. See Table 16. RSAL[i] Bus Frame RSALFR[i] Status Time Slot # Bit Position High Low (See Figure 17 144 Table 16 Content 1 Generated RDI EED 4 DSD 5 K1 Unstable 6 K2 Unstable ...
Page 145
... Frame pulse input TSALFR[i] indicates the expected presence of RDI at TSAL input repeated every 125 µs. — The Intel IXF6048 latches the data on the TSAL pin, using the input timing signals. As TSALCK[i] might not be synchronous with the transmit frame rate, some information may be lost once in a while, due to the frequency deviation ...
Page 146
... This detected default sets a maskable interrupt that can be accessed via global register TALBINT. When TSAL[i] is configured as a codirectional interface, Intel IXF6048 detects the absence of clock (TSALCK[i]) and/or framing pulse (TSALFR[i]) on the incoming timings input framing pulse is detected within 250 µ ...
Page 147
... As it can process four independent paths (four channels), Intel IXF6048 provides up to four RPAL interfaces (one per channel). For each channel, RPAL[i] provides the following detected alarms and information: — ...
Page 148
... RPAL[i] may also be used as a ring port by being connected directly to the transmit alarm port (TPAL input) of another Intel IXF6048 chip, to externally feedback the path RDI (HP-RDI) and path REI (HP-REI) information. In this case, the chip’s internal feedback of the remote defects is disabled. For this purpose, it provides: — ...
Page 149
... Mbit/s SONET/SDH Cell/Packet Interface — Intel IXF6048 Figure 19. Receive Path Alarm Serial Bus Timing Receive Path Alarm Serial Bus Timing Output frame RPOHFR[i] pulse RPAL[i] Output data Time Slot #1 Time Slot #2 Output clock RPOHCK[i] (576 KHz) RPOHFR[i] Input/Output frame pulse ...
Page 150
... Intel IXF6048 — 51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface Table 18. RPAL[i] Bus Frame RPOHFR[i] Status Time Slot # Bit Position High Low (See Figure 19 150 Content 1 Server Defect (LOP or AU-AIS) I 2:5 B3 Encoded Error/Generated REI [3:0] 7 Generated RDI[2] 8 Generated RDI[1:0] 1 RDI Spare 2 AU-AIS 3 LOP ...
Page 151
... Frame pulse input TPALFR[i] indicates the expected presence of “Server Defect” at TPAL input repeated every 125 µs. — The Intel IXF6048 latches the data on the TPAL pin, using the input timing signals. As TPALCK[i] might not be synchronous with the transmit VC rate, some information may be lost ...
Page 152
... Intel IXF6048 — 51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface . Table 19. TPAL[i] Bus Frame TPOHFR[i] Status Time Slot # Bit Position High Low 5 6 (See Figure 20 Figure 20. Transmit Path Alarm Serial Bus Timing Transmit Path Alarm Serial Bus Timing Input/Output TPOHFR[i] frame pulse TPAL[i] ...
Page 153
... RRD Input Data bit Data bit Data bit Data Communication channel 4.5.5 D12 Data Communication Channel For each multiplex section processed in the Intel IXF6048 (up to four), the interface is described below. Datasheet Data bit Data bit Data bit Data bit Data bit ...
Page 154
... Data bit Data Communication channel 4.5.5.3 E1, E2, and F1 Section Orderwire Channel The interface of each STS/STM aggregate processed in the Intel IXF6048 (up to four) is described below. 4.5.5.3.1 Transmit Side Access ( — Data inputs are TROW[i], TMOW[i], and TDOW[i]. — Clock reference is TOWC[i]. This 64-KHz signal is a square wave. Its phase, relative to the data transition, may be inverted via global configuration register OCPCNF, bit Pol_TOWC ...
Page 155
... Mbit/s SONET/SDH Cell/Packet Interface — Intel IXF6048 Figure 25. Transmit Orderwire E1, E2, and F1 Timing Transmit multiplex & regenenerator Section OverHead Serial Orderwire Timing (E1, F1, and E2) Output clock TOWC (64 KHz) Output frame byte TOWBYC clock (8 KHz) Configuration bit OWPlsCnf = 0 (register OHPCNF) and configuration bit Pol_TOWC = 0 (register OCPCNF) ...
Page 156
... Intel IXF6048 — 51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface 4.5.5.4 F2 and F3 Path Orderwire Channel For each path processed in the Intel IXF6048 (up to four), the interface is described below. 4.5.5.4.1 Transmit Side Access ( — Data inputs are TPOW1 and TPOW2. — Clock reference is TPOWC. This 64-KHz signal is a square wave. Its phase, relative to the data transition, may be inverted via global configuration register OCPCNF, bit Pol_TOWC ...
Page 157
... Mbit/s SONET/SDH Cell/Packet Interface — Intel IXF6048 Figure 28. Receive F2 and F3 Orderwire Timing Receive Path OverHead Serial Orderwire Timing (F2 and F3) Output clock RPOWC (64 KHz) Output frame byte RPOWBYC clock (8 KHz) Configuration bit OWPlsCnf = 0 (register OHPCNF) and configuration bit Pol_ROWC = 0 (register OCPCNF) ...
Page 158
... I.432 specifications by implementing all the Transmission Convergence Sublayer (TCS) functions necessary to adapt the service offered by the SONET/SDH physical layer to the service required by the ATM layer. Intel IXF6048 also implements a GFC halt function, in accordance with ITU-T Recommendations I.150 and I.361. the SONET SPE and the ATM cell format, respectively. ...
Page 159
... HEC-Based Cell Delineation The RACP performs cell delineation based on HEC correct calculations in accordance with ITU-T I.432. Intel IXF6048 offers some additional optional features to this standard process. The following describes the Intel IXF6048 cell delineation process. The HEC is a CRC-8 calculation over the first 4 bytes of the ATM cell header based on the ...
Page 160
... Intel IXF6048 — 51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface Figure 31. Cell Delineation State Diagram ALPHA consecutive (cell-by-cell check) 5.1.1.1 HEC Verification and HEC-Based Cell Filtering Normally, while in the PRESYNC state, no ATM cells are accepted. However, configuration bit RcvPRESYNCCnf (channel register R_ACPCNF) allows passing (writing into the receive FIFO) the correct ATM cells received while in the PRESYNC state ...
Page 161
... Intel IXF6048 allows the software to monitor the incoming Generic Flow Control (GFC) bits to determine the remote device configuration: controller device, controlled device GFC functions implemented. When the GFC is enabled in the system, Intel IXF6048 can be configured as a controlled or a controlling device. When configured as a controlled device, every time a cell is received with the “ ...
Page 162
... ATM-cell stream on the corresponding SPE. The FIFO memory is 32/256- cell deep in the first channel and 32-cell deep in the other three channels. When Intel IXF6048 is configured as a Single transceiver (OC-48c/STM-12c (concatenated)), only one TACP is active. It reads the ATM Layer cells from a 32/256-cell deep FIFO memory and maps them as a continuous ATM-cell stream on the outgoing SPE ...
Page 163
... T_ACELLCNT). — The number of idle cells generated and mapped into the transmitted SONET/SDH frames are counted in a 24-bit counter. Intel IXF6048 only counts the idle cells inserted by the cell rate decoupling process, not the idle/unassigned cells inserted by the Generic Flow Control function (channel register T_ICELLCNT). ...
Page 164
... ATM cell stream—only one channel is enabled and it connects to the interface using 256-cell FIFO memory (selectable). — When Intel IXF6048 is configured as a quad transceiver, four physical ports single non-concatenated transceiver—a single physical port transporting four independent ATM cell streams— ...
Page 165
... Mbit/s SONET/SDH Cell/Packet Interface — Intel IXF6048 Figure 33. Cell Rate Decoupling FIFOs in ATM-UTOPIA Multi-Channel Configuration RACP Channel #0 RACP Channel #1 RACP Channel #2 RACP Channel #3 Single Non-Concatenated or Quad Concatenated Line Side TACP Channel #0 TACP Channel #1 TACP Channel #2 TACP Channel #3 Figure 34. Cell Rate Decoupling FIFO in ATM-UTOPIA Single-Channel Configuration ...
Page 166
... Channel #2 RACP Channel #3 Single Non-Concatenated or Quad Concatenated Line Side TACP Channel #0 TACP Channel #1 TACP Channel #2 TACP Channel #3 Intel IXF6048 can share the UTOPIA interface with other PHY devices. 166 Rx ATM UTOPIA 32/256-cell L3/L2/L1 RXDATA_0[7:0] FIFO Interface #0 Rx ATM UTOPIA 32-cell FIFO ...
Page 167
... Mbit/s SONET/SDH Cell/Packet Interface — Intel IXF6048 Figure 36. ATM-UTOPIA Multiple Physical Device Mode 6.1 Data Bus Width and ATM Cell Data Structure The transmit data bus width and receive data bus width can be set independently. The receive data bus width is configured by setting RcvUMode[1:0] in global register R_UICNF. ...
Page 168
... Intel IXF6048 — 51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface Table 20. UTOPIA Receive Data Bus Width RcvUMode[1:0] '00' '01' '10' '11' The transmit data bus width is configured by setting XmtUMode[1:0] in global register T_UICNF. Inputs TXDATA[31:0] are always part of the UTOPIA interface, whereas, TXDATA[63:32] use inputs from the TTL line side interface or from overhead ports (see the pinout description). ...
Page 169
... Mbit/s SONET/SDH Cell/Packet Interface — Intel IXF6048 Table 21. UTOPIA Transmit Data Bus Width XmtUMode[1:0] '00' '01' '10' '11' The ATM cells are transferred using one of eight possible formats: • 64-bit × 7-word • 32-bit × 13-word • 32-bit × 14-word • 16-bit × 26-word • ...
Page 170
... Intel IXF6048 — 51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface The receive ATM cell structure is configured by setting RcvCellStruct in channel register R_UICHCNF; the transmit ATM cell structure is configured by setting XmtCellStruct in channel register T_UICHCNF. When the receive (transmit) interface is configured to use a 64-bit wide data bus, the value of RcvCellStruct (XmtCellStruct) is ignored and the interface transfers a single 56- byte cell format: • ...
Page 171
... Mbit/s SONET/SDH Cell/Packet Interface — Intel IXF6048 Figure 38. 13-Word ATM Cell Structure (32-Bit UTOPIA Interface) Figure 39. 14-Word ATM Cell Structure (32-Bit UTOPIA Interface) Figure 40. 26-Word ATM Cell Structure (16-Bit UTOPIA Interface) Datasheet Bit 31 Word Word 2 Payload 1 Payload 2 Payload 3 Word 3 Payload 5 ...
Page 172
... Intel IXF6048 — 51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface Figure 41. 27-Word ATM Cell Structure (16-Bit UTOPIA Interface) Figure 42. 52-Word ATM Cell Structure (8-Bit UTOPIA Interface) Figure 43. 53-Word ATM Cell Structure (8-Bit UTOPIA Interface) 172 Bit 15 Bit 0 Word Word Word 3 Unused Unused Word 4 ...
Page 173
... Mixed POS and ATM Configuration When Intel IXF6048 is configured as a Quad transceiver, four Physical ports Single non- concatenated transceiver—a single Physical port transporting four independent streams—it is possible to have channels operating in ATM mode and channels operating in POS mode, both sharing the same interface with the link layer device ...
Page 174
... IXF6048 shares the receive interface with other PHY devices. • When RcvMPhyDevCnf = '0', the receive outputs RXDATA, RXSOF, RXPRTY, and RXFA are always driven. This setting can be used when Intel IXF6048 is the only PHY device in the receive interface. The direct indication outputs RXFA_i ( can be configured to be driven always or driven only when RXADDR matches the programmed device address ...
Page 175
... Mbit/s SONET/SDH Cell/Packet Interface — Intel IXF6048 • RcvUWidth[1:0] = '10' (32-bit interface) • RcvCellStruct = '1' (14-word cell data structure) • RcvDRCnf = '1' (2 clock cycle decode-response time) • RcvMPhyDevCnf = '0' (single PHY device) Figure 48 shows an example where the receive interface has been configured as a 32-bit MPHY device ...
Page 176
... Single-Device/Multiple-Device Configuration Intel IXF6048 can be configured to operate as the only device in the interface (driving the outputs always) or sharing the interface with other PHY devices (driving the outputs only when it is selected). This feature can be configured independently in the receive and transmit directions. ...
Page 177
... XmtDRCnf = '0' (1 clock cycle decode-response time) • XmtMPhyDevCnf = '1' (multiple PHY device) 6.5 ATM-UTOPIA Level 3/Level 2 Compatibility Intel IXF6048 operates according to the ATM Forum UTOPIA Level 3 specification by using the following settings: • 32-bit data bus • 52-byte or 56-byte ATM cell data structure • ...
Page 178
... ATM cell data structure • 1 clock cycle decode-response configuration • Multiple-device mode Intel IXF6048 operates according to the UTOPIA (Level 1) specification by using the following settings: • 8-bit data bus • 52-byte or 53-byte ATM cell data structure • ...
Page 179
... Mbit/s SONET/SDH Cell/Packet Interface — Intel IXF6048 Figure 45. Transmit ATM-UTOPIA Interface as a Single PHY Device, 64-Bit Data Bus, and 56- Byte Cell Data Structure (ATM-UTOPIA Level 3) TXCLK TXSOC TXDATA TXENB ch2 ch3 ch1 ch0 ch2 TXADDR ch2 ch3 ch1 ch0 TXPFA ...
Page 180
... Intel IXF6048 — 51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface Figure 47. Transmit ATM-UTOPIA Interface as a Single PHY Device, 32-Bit Data Bus, and 56- Byte Cell Data Structure (ATM-UTOPIA Level 3 Mode) TXCLK TXSOC w10 w11 w12 w13 w14 TXDATA TXENB TXADDR ch2 ch0 ch1 ch1 ...
Page 181
... Mbit/s SONET/SDH Cell/Packet Interface — Intel IXF6048 Figure 49. Transmit ATM-UTOPIA Interface as a Multiple PHY Device, 32-Bit Data Bus, and 56- Byte Cell Data Structure TXCLK TXSOC w12 w13 w14 w1 TXDATA Z TXENB 1FH ch1 1FH ch2 1FH TXADDR ch2 ch1 TXPFA channel 0 ...
Page 182
... Intel IXF6048 — 51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface Figure 51. Transmit ATM-UTOPIA Interface as a Single PHY Device, 16-Bit Data Bus, and 54- Byte Cell Data Structure TXCLK TXSOC w23 w24 w25 w26 w27 TXDATA TXENB ch2 ch3 ch1 ch0 ch3 TXADDR ch2 ch3 ...
Page 183
... Mbit/s SONET/SDH Cell/Packet Interface — Intel IXF6048 Figure 53. Transmit ATM-UTOPIA Interface as a Multiple PHY Device, 16-Bit Data Bus, and 54- Byte Cell Data Structure (ATM-UTOPIA Level 2 Mode) TXCLK TXSOC w24 w25 w26 w27 XX TXDATA TXENB ch2 1FH ch1 1FH ch2 TXADDR ...
Page 184
... For POS packet sizes (not including the flag byte) that equal (in other words, 50, 54, 58, …, 65534, 65538, 65542), where integer from 12 to 16385, the Intel IXF6048 will add one extra byte internally and, therefore, reduce the overall throughput (100 / (the POS packet size + 3))% which is 1 ...
Page 185
... HDLC controllers extracts the incoming HDLC frames from the corresponding SPE, and writes the POS-packets into a FIFO memory. The FIFO memory is 16-Kbyte deep in the first channel and 2- Kbyte deep in the other three channels. When Intel IXF6048 is configured as a Single OC-48c/ STM-12c (concatenated) transceiver, only one HDLC controller is active, extracting the incoming HDLC frames from the SPE and writing the POS-packets into a 16-Kbyte deep FIFO memory ...
Page 186
... Intel IXF6048 — 51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface 7.1.1 SPE Descrambling Intel IXF6048 performs self-synchronous descrambling of the incoming HDLC frames (the incoming SPE bytes) using the polynomial X HDLC frames are processed (frame delineation, byte destuffing, etc.). The self-synchronous descrambling can be disabled by setting RcvDescrEn = '0' (register R_PHCCNF). ...
Page 187
... Mbit/s SONET/SDH Cell/Packet Interface — Intel IXF6048 7.1.6 FCS Verification The Frame Check Sequence (FCS) field is calculated over all bits of the Address, Control, Protocol, Information, and Padding fields, not including the Flag Sequences nor the FCS field itself. The FCS field is checked after Control Escape removal (after byte destuffing). The FCS is received least significant octet first, which contains the coefficient of the highest term ...
Page 188
... The number of received frames not marked as errored (“good frames”) are counted in a 27-bit counter (register R_FRMCNT). • The number of bytes received are counted in a 29-bit counter (register R_BYTECNT). Intel IXF6048 can be configured to count all the bytes written into the FIFO (good frames + frames marked as errored) or only the bytes received within good frames. ...
Page 189
... HDLC controllers reads the POS-packets from a FIFO memory (16-Kbyte deep in the first channel and 2-Kbyte deep in the other three), encapsulates the data into the generated HDLC frames, and maps the HDLC frames into the corresponding SPE. When Intel IXF6048 is configured as a Single OC-48c/STM-12c (concatenated) transceiver, only one HDLC controller is active, reading the user packets from a 16-Kbyte deep FIFO memory and mapping the generated HDLC frames into the outgoing SPE ...
Page 190
... Intel IXF6048 — 51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface 7.2.3 FCS Generation/Insertion The Frame Check Sequence (FCS) field is calculated over all bits of the Address, Control, Protocol, Information, and Padding fields, not including the Flag Sequences nor the FCS field itself. The FCS field is calculated before Control Escape insertion (before byte stuffing). The FCS is transmitted least significant octet first, which contains the coefficient of the highest term ...
Page 191
... ATM mode and channels in POS mode. The POS-UTOPIA interface connects a Link Layer device to the Intel IXF6048 (a Physical Layer device). The POS-UTOPIA interface is an extension of the ATM industry standard UTOPIA, adapted to support the transfer of variable length packets. ...
Page 192
... HDLC frame stream), only one channel is enabled and connected to the interface using 16-Kbyte FIFO memory (selectable). • When Intel IXF6048 is configured as a Quad transceiver (four Physical ports Single non-concatenated transceiver (a single Physical port transporting four independent HDLC frame streams), channel #0 is connected to the interface using a 16-Kbyte FIFO memory while channels #1, #2, and #3 use a 2-Kbyte FIFO memory ...
Page 193
... Mbit/s SONET/SDH Cell/Packet Interface — Intel IXF6048 Figure 56. POS-UTOPIA Physical Layer/Link Layer Rate Decoupling FIFOs in Multi-Channel Configuration Single Non-Concatenated or Quad Concatenated Line Side Figure 57. POS-UTOPIA Physical Layer/Link Layer Rate Decoupling FIFO in Single-Channel Configuration Channel #0 Single Concatenated Line Side Channel #0 Datasheet ...
Page 194
... Intel IXF6048 — 51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface Figure 58. Four Independent POS-UTOPIA Interfaces 194 Rx POS RPOSC 2/16 KB UTOPIA Channel #0 FIFO L3/L1 Interface #0 Rx POS RPOSC UTOPIA 2 KB FIFO Channel #1 L3/L1 Interface #1 Rx POS RPOSC UTOPIA 2 KB FIFO Channel #2 L3/L1 Interface The data lines could have #2 been 16-bit wide ...
Page 195
... Mbit/s SONET/SDH Cell/Packet Interface — Intel IXF6048 8.1 Data Bus Width and Packet Data Structure The transmit data bus width and receive data bus width can be set independently. The receive data bus width is configured by setting RcvUMode[1:0] in global register R_UICNF. Outputs RXDATA[31:0] are always part of the UTOPIA interface whereas RXDATA[63:32] use outputs from the TTL line side interface or from overhead ports (see the pinout description) ...
Page 196
... Intel IXF6048 — 51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface : Table 25. UTOPIA Transmit Data Bus Width XmtUMode[1:0] '00' '01' '10' '11' The POS-UTOPIA interface offers three different POS-packet formats. The first format transports the Information field of the HDLC frame. This format is selected by setting RcvACPass = '0' and RcvFCSPass = '0' in register R_PHCCNF. In transmission, this format is selected by setting XmtACPass = '0' in register T_PHCCNF ...
Page 197
... Mbit/s SONET/SDH Cell/Packet Interface — Intel IXF6048 Figure 59. POS-Packet Format (1-byte) FLAG (7EH) Figure 60, Figure 61, the POS-UTOPIA interface (transmit and receive directions) for the different data bus widths. The most significant bit of a word is the first received bit. The first word of the data structure (word one) in the RXDATA (TXDATA) bus is coincident with the RXSOF (TXSOF) indication ...
Page 198
... Intel IXF6048 — 51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface Figure 61. POS-Packet Data Structure Using the 32-Bit UTOPIA Interface Figure 62. POS-Packet Data Structure Using the 16-Bit UTOPIA Interface Figure 63. POS-Packet Data Structure Using the 8-Bit UTOPIA Interface 8.2 Receive POS-UTOPIA Interface 8.2.1 Port Selection Mode The receive POS-UTOPIA interface can be configured to operate as the ATM-UTOPIA interface (using a port selection cycle simple memory mapped device ...
Page 199
... Mbit/s SONET/SDH Cell/Packet Interface — Intel IXF6048 RXENB changes from '1' to '0'. Once the port is selected (RXENB = '0'), the receive address RXADDR[4:0] can take any value (FIFO status polling using RXPFA). • When configuration bit RcvSelMode = '1' (global register R_UICNF), the receive POS- UTOPIA interface is controlled as a memory mapped device ...
Page 200
... Single-Device/Multiple-Device Configuration Intel IXF6048 can be configured to operate as the only device in the interface (driving the outputs always) or sharing the interface with other PHY devices (driving the outputs only when it is selected). This feature can be configured independently in the receive and transmit directions. ...