RCLXT16706FE Intel, RCLXT16706FE Datasheet - Page 310

• Manufacturer Part Number: RCLXT16706FE
• Manufacturer: Intel

Specifications of RCLXT16706FE

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (max): 3.63V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Not Compliant

Intel IXF6048 — 51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface
310
Bit
8:6
4:3
9
5
XmtGFCcontrolled
XmtGFCCnt[2:0]
XmtReadEn
XmtHErrCnf
Name
XmtGFCcontrolled configures Intel IXF6048 as a controlled device.
When XmtGFCcontrolled is set to logic one, the transmit ATM cell
processor will:
The XmtGFCcontrolled and XmtGFCcontroller bits must not be
set to logic one simultaneously.
XmtGFCCnt[2:0] are used only by the transmitter when Intel
IXF6048 is configured as a controller device (XmtGFCcontroller =
'1'). XmtGFCCnt[2:0] indicates how many ATM cells are sent with
the halt bit set to logic one (GFC[3] = '1') for every ATM cell sent
with the halt bit set to logic zero:
XmtGFCCnt[2:0]:
'000' = GFC[3] is never set to logic one
'001' = GFC[3] is '1' in 50% of the transmitted cells.
'010' = GFC[3] is '1' in 66% of the transmitted cells.
……
'111' = GFC[3] is '1' in 87.5% of the transmitted cells.
XmtReadEn disables the reading of ATM Layer cells from the
transmit ATM FIFO.
'0' = The transmit ATM cell processor does not read cells from the
transmit FIFO (even if the FIFO contains complete ATM cell(s))
and maps idle cells into the SPE.
'1' = The transmit ATM cell processor operates normally, reading
ATM cells from the transmit FIFO (if the FIFO contains complete
ATM cell(s)).
XmtReadEn should not be used for transmit Flow Control.
Configuration bits XmtGFCcontrolled and XmtGFCCnt[2:0] offer a
better way to do that.
XmtHErrCnf[1:0] configures the insertion of errors into the
transmitted ATM cells:
'00' = Reserved.
'01' = Reserved.
'10' = Correctable errors are inserted in the transmitted cells when
XmtHErrEn is set to logic one.
'11' = Multiple uncorrectable errors are inserted in the transmitted
cells when XmtHErrEn is set to logic one.
When a correctable error is inserted, the most significant bit (first
transmitted bit) of the HEC sequence is inverted prior to
transmission.
When an uncorrectable error is inserted, the eight bits of the HEC
sequence are inverted prior to transmission.
1. Set the controlled-bit (GFC[0]) to logic one in the GFC[3:0] field,
2. Enable the GFC halt monitoring function. Every time an ATM
in all the transmitted cells.
cell with the halt-bit (GFC[3]) set to logic one is received, an
unassigned cell is inserted in the transmit stream.
Description
Type
R/W
R/W
R/W
R/W
Datasheet
Default
'000'
'00'
'0'
'1'