RCLXT16706FE Intel, RCLXT16706FE Datasheet - Page 255

• Manufacturer Part Number: RCLXT16706FE
• Manufacturer: Intel

Specifications of RCLXT16706FE

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (max): 3.63V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Not Compliant

11.3.8
Datasheet
15:8
Bit
5:0
Bit
7:0
7
6
XmtFIFORst
XmtCellStruct
XmtCADeassert [5:0]
Unused
XmfFDCnf[7:0]
T_UIFDP—Transmit UTOPIA Interface FIFO Depth ((0cc)41H)
Name
Name
51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface — Intel IXF6048
XmtFIFORst resets the transmit FIFO.
'0' = The transmit FIFO operates normally.
'1' = The FIFO is emptied and any following write commands are
disregarded. As soon as a logic zero is written into XmtFIFORst,
the UTOPIA interface accepts new writes, after receiving the first
start of frame (TXSOF input).
XmtCellStruct selects the cell data structure used in the transmit
ATM-UTOPIA interface:
'0' = No extra words are used between the first four ATM cell
header bytes (no HEC field) and the first ATM cell payload byte.
Depending on the data bus width configuration, that corresponds
to a cell data structure of 7 words (64-bit interface), 13 words (32-
bit interface), 26 words (16-bit interface), or 52 words (8-bit
interface).
'1' = An extra word (unused word) is used between the first four
ATM cell header bytes (no HEC field) and the first ATM cell
payload byte. Depending on the data bus width configuration, that
corresponds to a cell data structure of 8 words (64-bit interface), 14
words (32-bit interface), 27 words (16-bit interface), or 53 words (8-
bit interface).
XmtCADeassert[5:0] configures when to deasserted TXPFA
(transmit polled cell available output), TXSFA (transmit selected
frame-available output), and TXFA_i (i = 0, 1, 2, 3, transmit direct
cell available outputs) in the transmit ATM-UTOPIA interface.
When the ATM cell being written into the UTOPIA interface is
stored in the last cell-slot available in the FIFO, each of these
outputs is deasserted three clock cycles after the TXCLK rising
edge that samples the word indicated by XmtCADeassert[5:0]: 1,
2, 3,… n-3 (n = 7, 13, 14, 52, 53). The value of n (number of words
of the cell) depends on the bus width and the cell structure.
Configuring XmtCADeassert[5:0] to an appropriate value ensures
that the ATM Layer device can detect that the current ATM cell is
going to fill up the transmit FIFO, four clock cycles (or more) before
writing the last word.
XmtFDCnf[7:0] configures the depth of the transmit FIFO when the
channel works in ATM mode. TXFA is deasserted when the
number of cells in the FIFO is greater than indicated by
XmfFDCnf[7:0].
If the configured FIFO depth is smaller than the real depth of the
FIFO, additional cells, after the configured depth is reached, are
written into the FIFO until the FIFO is full.
For channels 1, 2, and 3, only XmtFDCnf[4:0] are used and
XmtFDCnf[7:5] are unused bits.
Description
Description
Type
Type
R/W
R/W
R/W
R/W
Default
Default
FFH
19H
'0'
'0'
255