RCLXT16706FE Intel, RCLXT16706FE Datasheet - Page 339

• Manufacturer Part Number: RCLXT16706FE
• Manufacturer: Intel

Specifications of RCLXT16706FE

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (max): 3.63V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Not Compliant

Datasheet
RXCLK_i frequency (i = 0, 1, 2, 3)
RXCLK_i duty cycle (i = 0, 1, 2, 3)
RXENB_i setup time to RXCLK_i (i = 0, 1, 2, 3)
RXENB_i hold time from RXCLK_i (i = 0, 1, 2, 3)
RXCLK_i rising edge to RXDATA_i[7:0], RXPRTY_i, RXSOF_i,
RXEOF_i, RXVAL_i, RXERR_i, and RXFA_i (i = 0, 1, 2, 3) propagation
delay
TXCLK_i frequency (i = 0, 1, 2, 3)
TXCLK_i duty cycle (i = 0, 1, 2, 3)
TXDATA_i[7:0], TXENB_i, TXSOF_i, TXEOF_i, TXPRTY_i, and
TXERR_i setup time to TXCLK_i (i = 0, 1, 2, 3)
TXDATA_i[7:0], TXENB_i, TXSOF_i, TXEOF_i, TXPRTY_i, and
TXERR_i hold time from TXCLK_i (i = 0, 1, 2, 3)
TXCLK_i rising edge to TXFA_i (i = 0, 1, 2, 3) propagation delay
Figure 90. Transmit UTOPIA Quad Interface Configured for 104 MHz Operation: 8-Bit Data
Table 46. Receive UTOPIA Quad Interface Timings for the Configurations Supporting 104
Table 47. Transmit UTOPIA Quad Interface Timings for the Configurations Supporting 104
Bus, Two Clock Cycle Decode-Response Delay and No High-Impedance Outputs
MHz Operation: 8-Bit Wide Data Bus, Two Decode-Response Clock Cycles and No
High-Impedance Outputs
MHz Operation: 8-Bit Wide Data Bus, Two Decode-Response Clock Cycles and No
High-Impedance Outputs
TXDATA_i[7:0], TXENB_i,
TXPRTY_i, TXERR_i
TXSOF_i, TXEOF_i
Parameter
Parameter
51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface — Intel IXF6048
TXCLK_i
TXFA_i
VALID OUTPUT
t
ul3Txsu
VALID INPUT
t
ul3Txpd
t
ul3Txh
Symbol
Symbol
t
t
t
t
D
t
D
t
ul3Rxsu
ul3Rxpd
ul3Txsu
ul3Txpd
f
f
ul3Rxh
ul3Txh
ul3Rx
ul3Tx
ul3Rx
ul3Tx
1/f
VALID OUTPUT
ul3Tx
VALID INPUT
Min
Min
2.0
0.5
2.0
0.5
30
30
1
1
Typ
Typ
Max
Max
104
104
70
70
6
6
MHz
MHz
Unit
Unit
ns
ns
ns
ns
ns
ns
%
%
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