RCLXT16706FE Intel, RCLXT16706FE Datasheet - Page 95

• Manufacturer Part Number: RCLXT16706FE
• Manufacturer: Intel

Specifications of RCLXT16706FE

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (max): 3.63V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Not Compliant

2.1.3
Datasheet
Receive ATM Cell Processor Block
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Insertion of DCC channels (D1-D3, D4 to D12) and orderwire channels (E1, E2, F1) either
from the dedicated serial ports (at 192-, 576- and 64-Kbit/s) or from the Transmit Section
serial OverHead bus (TSOH).
Calculation (after scrambling) and insertion of multiplexer section BIP-8/24/96/392 (B2 bytes)
and regenerator section BIP-8 (B1).
Serial access and insertion of any other SOH byte via the Transmit Section OverHead bus
input (TSOH).
Data scrambling and multiplexing of the first RSOH row: Microprocessor programmable 1-,
16- (with CRC-7), or 64-byte section Trace Identifier (J0 byte) insertion, microprocessor
configurable Z0 bytes insertion, and framing bytes (A1, A2) insertion.
Microprocessor programmable Path unequipped generation. Microprocessor programmable
AIS insertion at the different layers (path, adaptation, section).
Microprocessor configurable option to pass through each received RSOH byte in repeater
mode.
The DCC channels may be provided via dedicated serial accesses at 192-Kbit/s (D1-D3) and
576-Kbit/s (D4 to D12). The section orderwires and user channels may be provided via 3
dedicated 64-Kbit/s serial ports (E1, E2, and F1). The path orderwires may be provided via 2
dedicated 64-Kbit/s serial ports (F2 and F3).
Transmitter diagnostic and test features: Microprocessor interface allows pointer movements,
NDF generation, B1, B2, B3, BIP inversion, A1 framing bytes inversion, and scrambler
disabling of B1, B2, BIP, or A1.
Demaps ATM cells from the received STS-48c/STM-16c/STS-48/STM-16/STS-12c/STM-4c/
STS-12/STM-4/STS-3c/STM-1/STS-1 signal.
HEC-based cell delineation and filtering using HUNT state, PRESYNCH state, SYNC state,
and the LCD defect.
Correction and Detection modes within SYNC state.
Single- and multiple-bit error detection.
Single-bit error correction if correction is enabled.
Cell payload self-synchronous descrambling.
Programmable filter for Idle/Unassigned cell detection and discarding.
Write control of four, independent, 32-cell deep, cell-rate decoupling, FIFO memories (Single
non-concatenated transceiver and Quad transceiver modes).
Write control of one, 256-cell deep, cell-rate decoupling, FIFO memory (Single concatenated
mode).
GFC bits monitored to determine the remote device configuration (controller device,
controlled device, or no GFC functions implemented). GFC halt bit monitored when
configured as a controlled device.
The number of cells that have been written into the receive FIFO (cells passing the configured
cell filter) are counted in a 24-bit counter.
The number of cells matching the Idle/Unassigned programmable filter are counted in an 24-
bit counter.
51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface — Intel IXF6048
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