RCLXT16706FE Intel, RCLXT16706FE Datasheet - Page 217

• Manufacturer Part Number: RCLXT16706FE
• Manufacturer: Intel

Specifications of RCLXT16706FE

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (max): 3.63V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Not Compliant

Datasheet
(000)06H
(000)07H
(000)08H
(0cc)09H
(0cc)0AH
(0cc)0BH
(000)0CH
(000)0DH
(000)0EH
(000)0FH
(000)10H
(000)11H
(000)12H
(000)13H
(000)14H
(000)1AH
(000)1BH
(000)1CH
(000)1DH
(000)1EH
(000)1FH
(000)20H
(000)21H
(000)70H
(000)71H
(0cc)60H
(0cc)61H
(000)50H
(000)51H
(0cc)40H
(0cc)41H
(0cc)42H
(0cc)43H
(000)72H
(000)52H
(000)73H
Table 26. Register Address Map (Sheet 2 of 6)
Address
ATMPOS_GIS
S_AIS
GOCNF
COCNF
R_COCNF
T_COCNF
OHPCNF
R_FPCNF
T_FPCNF
OCPCNF
ICPCNF1
ICPCNF2
ICMR1
ICMR2
NCMODECNF
PRBSINT
PRBSINTEN
TALBINT
TALBINTEN
LSPCNF
LSPINT
LSPINTEN
MISC_GIS
R_UICNF
R_UIIML
R_UICHCNF
R_PWM
T_UICNF
T_UIIML
T_UICHCNF
T_UIFDP
T_NFPWM
T_NEPWM
R_UTOINT
T_UTOINT
R_UTOINTEN
Mnemonic
51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface — Intel IXF6048
ATM and POS Global Interrupt Source Register
Channel Operational Configuration Register
Miscellaneous Global Interrupt Source Register
Receive UTOPIA Interface Channel Configuration
Receive Programmable Watermark
SDH/SONET Receive AIS Register
Global Operational Configuration Register
Receive Channel Operational Configuration Register
Transmit Channel Operational Configuration Register
Overhead Ports Configuration Register
Receive Frame Pulse Configuration Register
Transmit Frame Pulse Configuration Register
Output Clock Polarity Configuration
Input Clock Polarity Configuration 1
Input Clock Polarity Configuration 2
Input Clock Monitoring Register 1
Input Clock Monitoring Register 2
Non-concatenated mode Configuration Register
PRBS Analyzer Interrupt Register
PRBS Analyzer Interrupt Enable Register
Transmit Alarm Bus Interrupt Register
Transmit Alarm Bus Interrupt Enable Register
Line Side Parity Configuration Register
Line Side Parity Interrupt Register
Line Side Parity Interrupt Enable Register
Receive UTOPIA Interface Configuration
Receive UTOPIA Interface Initiation Minimum Level
Transmit UTOPIA Interface Configuration
Transmit UTOPIA Interface Initiation Minimum Level
Transmit UTOPIA Interface Channel Configuration
Transmit UTOPIA Interface FIFO Depth
Transmit Near Full Programmable Watermark
Transmit Near Empty Programmable Watermark
Receive UTOPIA Interface Interrupt Register
Transmit UTOPIA Interface Interrupt Register
Receive UTOPIA Interface Interrupt Enable Register
UTOPIA Interface Registers
Register Name
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
R
R
R
R
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