RCLXT16706FE Intel, RCLXT16706FE Datasheet - Page 250

• Manufacturer Part Number: RCLXT16706FE
• Manufacturer: Intel

Specifications of RCLXT16706FE

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (max): 3.63V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Not Compliant

Intel IXF6048 — 51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface
250
Bit
5:0
7
6
RcvFIFORst
RcvCellStruct
RcvCADeassert[5:0]
Name
RcvFIFORst resets the receive FIFO:
'0' = The receive FIFO operates normally.
'1' = The FIFO is emptied and any further read command is
disregarded. All the frames (in POS mode) or cells (in ATM mode)
received while RcvFIFORst = '1' are lost but it are not considered a
FIFO overflow.
RcvCellStruct selects the cell data structure used in the receive
ATM-UTOPIA interface:
'0' = No extra words are used between the first four ATM cell
header bytes (no HEC field) and the first ATM cell payload byte.
Depending on the data bus width configuration, that corresponds to
a cell data structure of 7 words (64-bit interface), 13 words (32-bit
interface), 26 words (16-bit interface), or 52 words (8-bit interface).
'1' = An extra word (unused word) is used between the first four
ATM cell header bytes (no HEC field) and the first ATM cell
payload byte. Depending on the data bus width configuration, that
corresponds to a cell data structure of 8 words (64-bit interface), 14
words (32-bit interface), 27 words (16-bit interface), or 53 words (8-
bit interface).
RcvCADeassert[5:0] configures when to deassert RXPFA (receive
polled cell available output) and RXFA_i (i = 0, 1, 2, 3, receive
direct cell available outputs) when the addressed channel works in
ATM mode.
When the ATM cell being read in the UTOPIA interface is the last
complete cell in the FIFO, each of these outputs are deasserted
when the word containing the cell byte indicated by
RcvCADeassert[5:0]: 1, 2, 3,… n. (n = 52, 53, 54, or 56). The value
of n (number of bytes of the cell) depends on the cell structure.
RcvCADeassert cannot be configured to zero.
Configuring RcvCADeassert[5:0] to an appropriate value ensures
that the ATM Layer device can detect that the current ATM cell is
the last cell in the FIFO, four clock cycles (or more) before reading
the last word.
Description
Type
R/W
R/W
R/W
Datasheet
Default
19H
'0'
'0'