RCLXT16706FE Intel, RCLXT16706FE Datasheet - Page 308

• Manufacturer Part Number: RCLXT16706FE
• Manufacturer: Intel

Specifications of RCLXT16706FE

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (max): 3.63V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Not Compliant

Intel IXF6048 — 51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface
11.11.9
308
15:12
Bit
11
10
9
8
7
6
5
4
3
2
1
0
Unused
RcvLCDSt
RcvOCDSt
RcvICellCntI
RcvACellCntI
RcvUHECntI
RcvCHECntI
RcvFifoOFCntI
RcvLCDI
RcvOCDI
RcvUHEI
RcvCHEI
RcvFifoOFI
R_ATMINT—Receive ATM Interrupt (and Status) Register ((1cc)2BH)
Name
The RcvLCDSt status bit shows the state of the cell delineation
process. When RcvLCDSt is high, the cell delineation process is in
the LCD (loss of cell delineation) state. When RcvLCDSt is low, the
cell delineation process is not in the LCD state. Register
R_LCDFLTR contains a programmable threshold for configuring
the transitions to/from the LCD state.
The RcvOCDSt status bit shows the state of the cell delineation
process. When RcvOCDSt is low, the cell delineation process is in
the SYNC state. When RcvOCDtS is high, the cell delineation
process is in the HUNT or PRESYNCH states.
RcvICellCntI sets to logic one when the “receive idle cell counter”
(register R_ICELLCNT) rolls over.
This interrupt bit clears automatically when this register is read.
RcvACellCntI sets to logic one when the “receive ATM cell counter”
(register R_ACELLCNT) rolls over.
This interrupt bit clears automatically when this register is read.
RcvUHECntI sets to logic one when the “receive ATM
uncorrectable HEC error counter” (register R_UHECNT) rolls over.
This interrupt bit clears automatically when this register is read.
RcvCHECntI sets to logic one when the “receive ATM correctable
HEC error counter” (register R_CHECNT) rolls over.
This interrupt bit clears automatically when this register is read.
RcvFifoOFCntI sets to logic one when the “receive ATM FIFO
overflow counter” (register R_CFOCNT) rolls over.
This interrupt bit clears automatically when this register is read.
RcvLCDI sets to logic one when the cell delineation process enters
or exits the LCD (loss of cell delineation) state.
This interrupt bit clears automatically when this register is read.
RcvOCDI sets to logic one when the cell delineation process enters
or exits the SYNC state.
This interrupt bit clears automatically when this register is read.
RcvUHEI sets to logic one when an ATM cell with an uncorrectable
header error is received.
This interrupt bit clears automatically when this register is read.
RcvCHEI sets to logic one when an ATM cell with a correctable
header error is received. This interrupt is activated regardless of
the configuration of RcvCorrectEn (register R_ACPCNF).
This interrupt bit clears automatically when this register is read.
RcvFifoOFI sets to logic one when a receive ATM FIFO overflow
occurs. This means the receive ATM cell processor can not write
an ATM cell because the receive ATM FIFO does not have
available space for a complete cell.
This interrupt bit clears automatically when this register is read.
Description
Type
R
R
R
R
R
R
R
R
R
R
R
R
Datasheet
Default
'0'
'0'
'0'
'0'
'0'
'0'
'0'
'0'
'0'
'0'
'0'
'0'