RCLXT16706FE Intel, RCLXT16706FE Datasheet - Page 230

• Manufacturer Part Number: RCLXT16706FE
• Manufacturer: Intel

Specifications of RCLXT16706FE

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (max): 3.63V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Not Compliant

Intel IXF6048 — 51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface
230
7:5
4:2
1:0
Bit
RcvCOCnf[2:0]
RcvIFMode[2:0]
RcvChMode[1:0]
Name
RcvCOCnf[2:0] configures the TTL receive output clocks (RPCO,
RPCO_i, and RSCO_i) as divided or flowed-through versions of
the received input clocks (RPCI_P/N, RPCI_Pi/Ni, RPCI, RPCI_i,
and RSCI_i):
2:0
'000' Receive input clock ÷ 1 (flow-through)
'001' Receive input clock ÷ 2
'010' Receive input clock ÷ 4
'011' Receive input clock ÷ 8
'100' Receive input clock ÷ 16
'101' Receive input clock ÷ 32
'110' 8-KHz clock
'111'
See the pin description for details.
RcvIFMode configures the type of line side interface used by the
receive channel:
'000' = 32-bit TTL
'001' = Reserved
'010' = 8-bit TTL
'011' = 1-bit TTL
'100' = 16-bit PECL
'101' = Reserved
'110' = Reserved
'111' = 1-bit PECL
NOTE: In order to use the line loop back mode (LineLoopBack =
NOTE: The 32-bit TTL and 16-bit PECL configurations can be
RcvChMode[1:0] configures the receive channel in one of the
following operational modes:
'00' = Test mode. The receive channel analyzes the incoming
SPE bytes using an X
Error detection is indicated using register PRBSINT. In this
configuration, no data is written into the UTOPIA receive FIFO.
'01' = Transparent mode. The receive channel does not perform
any processing of the SPE bytes. The full SPE is written into the
UTOPIA receive FIFO (allowing the use of an external SPE
analyzer).
'10' = ATM Mode (UTOPIA)
'11' = POS Mode (UTOPIA like)
TTL Receive Output Clock
tristated
'1', register COCNF) or to clock the transmit channel by
using the receive channel timing reference
(XmtTimRef[1:0] = '01', register T_COCNF), the
configuration values RcvIFMode[2:0] and
XmtIFMode[2:0] (register T_COCNF) must match.
used only when Intel IXF6048 is configured as a single
transceiver. In this mode (single transceiver
configuration), the configuration values for channels 1, 2
and 3 are ignored.
15
+ X
Description
14
+ 1 linear feedback shift register.
Type
R/W
R/W
R/W
Datasheet
Default
'100'
'111'
'10'