RCLXT16706FE Intel, RCLXT16706FE Datasheet - Page 59

• Manufacturer Part Number: RCLXT16706FE
• Manufacturer: Intel

Specifications of RCLXT16706FE

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (max): 3.63V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Not Compliant

Datasheet
Table 4.
Pin Description (Sheet 45 of 66)
RXVAL_0
RXVAL_1
RXVAL_2
RXVAL_3
NOTE: See notes 1, 2, and
Pin Name
51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface — Intel IXF6048
F13
E15
A23
D24
Pin
LVTTL
Output
12 mA
Type
3
at the end of the table.
Receive Valid Data Output. RXVAL_i (i = 0, 1, 2, 3) is the active-high
data validation signal. RXVAL_i validates the receive output signals for
interface #i: RXDATA_i, RXSOF_i, RXEOF_i, and RXERR_i. Note that
RXPRTY_i (i = 0, 1, 2, 3) is valid independently of RXVAL_i. RXVAL_i (i
= 0, 1, 2, 3) is used only in POS mode; in ATM mode, this output is held
in high impedance (see RcvTestOen in register R_UICNF).
RXVAL_i (i = 0, 1, 2, 3) is always driven.
Depending on the configuration on RcvValCnf (register R_UICNF),
RXVAL_i (i = 0, 1, 2, 3) can be used in two different ways:
RcvValCnf = '0'
RXVAL_i (i = 0, 1, 2, 3) assertion and deassertion is based only on the
status of the receive FIFO #i. RXVAL_i is deasserted when attempting to
read an empty FIFO (receive FIFO underflow). When the Data Link
Layer device tries to read an empty receive FIFO #i, the read command
is disregarded, the receive FIFO #i is not modified and the Data Link
Layer device must ignore the value of the RXDATA_i, RXSOF_i,
RXEOF_i, and RXERR_i. The receive FIFO underflow is not considered
an error (no data is lost).
RcvValCnf = '1'
RXVAL_i (i = 0, 1, 2, 3) is used in the same way as for RcvValCnf = '0'
(invalidation of RXDATA_i, RXSOF_i, RXEOF_i, and RXERR_i if FIFO
#i is empty). In addition, RXVAL_i is also deasserted after reading the
last byte of a packet, i.e., the next byte (start of the next packet) is not
read from FIFO #i. When RXVAL_i is deasserted, the conditions FIFO-
empty and end-of-packet are differentiated using RXEOF_i. This
configuration allows the Link Layer device to synchronize with the packet
boundaries.
RXVAL_i (i = 0, 1, 2, 3) is updated on the rising edge of RXCLK_i.
• If RXVAL_i (i = 0, 1, 2, 3) has been deasserted due to an interpacket
• If RXVAL_i (i = 0, 1, 2, 3) is deasserted because FIFO #i is empty
boundary (when RcvValCnf = '1'), the Data Link Layer device must
deassert RXENB_i during a clock cycle (or more) before reading the
next packet. Otherwise, the receive FIFO will be blocked.
(RcvValCnf = '0' or '1'), the Data Link Layer device is not required to
deassert RXENB_i. Once new data is received and written into FIFO
#i, the Data Link Layer device can continue reading.
Description
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