RCLXT16706FE Intel, RCLXT16706FE Datasheet - Page 100
RCLXT16706FE
Manufacturer Part Number
RCLXT16706FE
Description
Manufacturer
Intel
Datasheet
1.RCLXT16706FE.pdf
(352 pages)
Specifications of RCLXT16706FE
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
2.97V
Operating Supply Voltage (max)
3.63V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Lead Free Status / Rohs Status
Not Compliant
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Intel IXF6048 — 51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface
3.0
100
Line Side Interface
Intel IXF6048’s Line Side Interface uses differential PECL I/O running at up to 155.52 MHz and
TTL I/O running at up to 77.76 MHz. The line side interface can be configured in the following
modes:
The Line Side Interface can be configured totally independently in the receive and transmit
directions. However, in order to use the Line Loopback mode or to clock a transmit channel with
the corresponding receive channel timing reference, it is necessary to configure the receive and
transmit line side interfaces in the same mode. These are the main configuration features of Intel
IXF6048 line side interface:
•
•
•
•
•
•
•
•
•
Single OC-48c or single OC-48 (2488 Mbit/s):
Single OC-12 (622 Mbit/s):
Single OC-3 (155 Mbit/s):
Quad OC-12c (4 × 622 Mbit/s):
Quad OC-3c (4 × 155 Mbit/s):
Quad OC-1 (4 × 51 Mbit/s):
Configuration bit QMode (register GOCNF) controls the configuration of the line side
interface I/O as a single parallel interface or as four independent serial interfaces.
When configured as a Single transceiver (QMode = '0'), configuration bits RcvIFMode[2:0]
(register R_COCNF) and XmtIFMode[2:0] (register T_COCNF) configure the receive and
transmit line side interfaces as a 16-bit PECL interface, an 8-bit PECL interface, a 1-bit PECL
interface, a 32-bit TTL interface, a 8-bit TTL interface, or a 1-bit TTL interface
(independently for each direction).
When configured as a Quad transceiver (QMode = '1'), configuration bits RcvIFMode[2:0]
(register R_COCNF) and XmtIFMode[2:0] (register T_COCNF) configure each receive and
transmit line side interface as a 1-bit PECL interface, an 8-bit TTL interface, or a 1-bit TTL
interface (independently for each direction and on each channel).
— 16-bit differential PECL parallel interface at 155.52 MHz
— 32-bit TTL parallel interface at 77.76 MHz
— 8-bit TTL parallel interface at 77.76 MHz
— 1-bit differential PECL serial interface at 155.52 MHz
— 8-bit TTL parallel interface at 19.44 MHz
— Four independent 8-bit TTL parallel interfaces at 77.76 MHz
— Four independent 1-bit differential PECL serial interfaces at 155.52 MHz
— Four independent 8-bit TTL parallel interfaces at 19.44 MHz
— Four independent 1-bit differential PECL serial interfaces at 51.84 MHz
— Four independent 1-bit TTL serial interfaces at 51.84 MHz
— Four independent 8-bit TTL parallel interfaces at 6.48 MHz
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