RCLXT16706FE Intel, RCLXT16706FE Datasheet - Page 111

• Manufacturer Part Number: RCLXT16706FE
• Manufacturer: Intel

Specifications of RCLXT16706FE

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (max): 3.63V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Not Compliant

4.4.1.1
Datasheet
RPDI_P/N[15:0]
TPCI/TCCI/TSCI
RSCI_P/N
Transmit Line
(Blue) Clock -
RSDI_P
RSDI_N
RLOCK
Selected
RPCI_P/N
Figure 7. SONET/SDH Receiver Blocks
Receive Line
Interface Side
Line Interface Processing
A filter for the RLOCK (Receiver Loss Of Synchronization) alarm input is provided by the line
interface circuit (register R_RSTC). The filtering on the RLOCK can be integrated over 128 or
4096 bits for OC-1/3 and over 512 or 16384 bits for OC-12/OC-48. A RLOCK status change is
indicated in register S_RG. In addition, Intel IXF6048 internally processes a configurable receiver
Loss Of Signal (LOS) detection based on data transition or all ‘0’s detection, configured via
register R_RSTC. LOS alarm is set when no transition (or all ‘0’s, if configured) occurs in the
incoming data for at least X µs (X is configurable to 20 or 25 µs) and cleared if two consecutive
framewords are detected and there is no LOS condition between (see register R_RSTC).
For each of the four channels, the interface block accepts a serial format input at RSDI_P/Ni in
OC-1/3 mode or an 8-bit parallel input format at RPDI_i[7:0] in OC-1/3/12 mode (four channel
operation). For single OC-48 channel operation, the input data may be parallel with an 8- or 16-bit
wide bus input at RPDI_P/N[15:0] or a 32-bit wide bus input at RPDI[31:0]. No specific order on
the 8-bit, 16-bit, or 32-bit is required for the Intel IXF6048 to operate. The parallel clock is input at
RPCI or RPCI_P/N, and the serial clock at RSCI_P/N.
The transmit clock is used for the selected transmit line (Blue) clock signal reference (if so
configured—TPCI/TCCI/TSCI):
An active RLOCK (external LOS) or internal LOS can have two consequent actions that can be
enabled or disabled (see register R_RSTC):
distribution
references
Interface
Interface
Parallel
•
•
Serial
Clock
and
Clock switches from receive clock (RPCI/RSCI) to selected transmit line reference (Blue)
clock (TPCI/TSCI/TCCI)
Insert AIS towards the ATM/POS demapping block from the RST section
51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface — Intel IXF6048
Receive side SONET / SDH Framer Block of AMAZON-A
Framer
Interface
Serial
DCC
Regenerator
receiver
Section
Orderwires
(Optional)
Interface
Serial
Alarms Serial
(Optional)
Interface
SOH &
Multiplexer section
Interface
Serial
DCC
receiver
LINE REI/RDI
Orderwire
(Optional)
Interface
Serial
Recovery
AU-4(c) /
Pointer
AU-3(c)
Orderwires
(Optional)
Higher order path
Interface
VC-4(c) / VC-3(c)
Serial
Receiver
PATH REI/RDI
(Optional)
Interface
POH &
Alarms
Serial
RDATA[31:0]
RCEN
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