LPC2420_60 NXP Semiconductors, LPC2420_60 Datasheet - Page 7
LPC2420_60
Manufacturer Part Number
LPC2420_60
Description
NXP Semiconductors designed the LPC2420/2460 microcontroller around a 16-bit/32-bitARM7TDMI-S CPU core with real-time debug interfaces that include both JTAG andembedded trace
Manufacturer
NXP Semiconductors
Datasheet
1.LPC2420_60.pdf
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NXP Semiconductors
Table 3.
LPC2420_60
Product data sheet
Pin Symbol
17
Row B
1
5
9
13
17
Row C
1
5
9
13
17
Row D
1
5
9
13
17
Row E
1
14
Row F
1
14
Row G
1
14
P1[5]/ENET_TX_ER/
P0[7]/I2STX_CLK/SCK1
P0[6]/I2SRX_SDA/
MCIPWR/PWM0[3]
P3[2]/D2
P1[1]/ENET_TXD1
P4[25]/WE
V
P2[0]/PWM1[1]/TXD1/
TRACECLK
P3[13]/D13
P3[9]/D9
V
/MAT2[1]
V
TRST
P3[11]/D11
P1[2]/ENET_TXD2/
MCICLK/PWM0[1]
SSEL1/MAT2[0]
P2[4]/PWM1[5]/
DSR1/TRACESYNC
P0[26]/AD0[3]/
AOUT/RXD3
P2[1]/PWM1[2]/RXD1/
PIPESTAT0
P0[25]/AD0[2]/
I2SRX_SDA/TXD3
P4[11]/A11
P3[5]/D5
n.c.
DD(3V3)
DD(3V3)
DD(3V3)
Pin allocation table
Pin Symbol
2
6
10
14
2
6
10
14
2
6
10
14
2
15
2
15
2
15
…continued
-
P3[10]/D10
V
P4[29]/BLS3/
MAT2[1]/RXD3
P3[19]/D19/
PWM0[4]/DCD1
-
TDI
P3[22]/D22/
PCAP0[0]/RI1
P3[21]/D21/
PWM0[6]/DTR1
P0[9]/I2STX_SDA/
MOSI1/MAT2[3]
-
P3[28]/D28/
CAP1[1]/PWM1[5]
P0[3]/RXD0
P1[16]/ENET_MDC
P1[7]/ENET_COL/
MCIDAT1/PWM0[5]
-
TCK
V
P3[4]/D4
P3[17]/D17/
PWM0[2]/RXD1
P0[24]/AD0[1]/
I2SRX_WS/CAP3[1]
P4[27]/BLS1
SSIO
SSIO
All information provided in this document is subject to legal disclaimers.
Rev. 6.1 — 22 September 2011
Pin Symbol
3
7
11
15
3
7
11
15
3
7
11
15
3
16
3
16
3
16
-
P3[1]/D1
P4[30]/CS0
P1[6]/ENET_TX_CLK/
MCIDAT0/PWM0[4]
P4[14]/A14
-
RTCK
P1[8]/ENET_CRS_DV/
ENET_CRS
P4[28]/BLS2/
MAT2[0]/TXD3
P3[18]/D18/
PWM0[3]/CTS1
-
TDO
V
V
P2[2]/PWM1[3]/
CTS1/PIPESTAT1
-
TMS
P2[3]/PWM1[4]/
DCD1/PIPESTAT2
P3[29]/D29/
MAT1[0]/PWM1[6]
P2[5]/PWM1[6]/
DTR1/TRACEPKT0
V
P2[7]/RD2/
RTS1/TRACEPKT2
DD(3V3)
DD(DCDC)(3V3)
DD(3V3)
Flashless 16-bit/32-bit microcontroller
LPC2420/2460
Pin Symbol
4
8
12
16
4
8
12
16
4
8
12
16
4
17
4
17
4
17
-
P3[0]/D0
P4[24]/OE
P0[4]/I2SRX_CLK/RD2/
CAP2[0]
P4[13]/A13
-
P0[2]/TXD0
P1[10]/ENET_RXD1
P0[5]/I2SRX_WS/TD2/
CAP2[1]
P4[12]/A12
-
P3[12]/D12
P3[8]/D8
V
P1[13]/ENET_RX_DV
-
P3[3]/D3
P2[6]/PCAP1[0]/
RI1/TRACEPKT1
DBGEN
P3[16]/D16/
PWM0[1]/TXD1
V
P4[10]/A10
SSCORE
DDA
© NXP B.V. 2011. All rights reserved.
7 of 86
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