mc68hc705v12 Freescale Semiconductor, Inc, mc68hc705v12 Datasheet - Page 160

• Manufacturer Part Number: mc68hc705v12
• Description: M68hc05-based Mcu Hc05 Freescale Semiconductor
• Manufacturer: Freescale Semiconductor, Inc

Byte Data Link Controller – Digital (BDLC–D)
14.6 BDLC Protocol Handler
Advance Information
NOTE:
During arbitration, or even throughout the transmitting message, when
an opposite bit is detected, transmission is stopped immediately unless
it occurs on the 8th bit of a byte. In this case, the BDLC automatically will
append up to two extra logic 1 bits and then stop transmitting. These two
extra bits will be arbitrated normally and thus will not interfere with
another message. The second logic 1 bit will not be sent if the first loses
arbitration. If the BDLC has lost arbitration to another valid message,
then the two extra logic 1s will not corrupt the current message.
However, if the BDLC has lost arbitration due to noise on the bus, then
the two extra logic 1s will ensure that the current message will be
detected and ignored as a noise-corrupted message.
The protocol handler is responsible for framing, arbitration, CRC
generation/checking, and error detection. The protocol handler
conforms to SAE J1850 Class B Data Communications Network
Interface.
Freescale assumes that the reader is familiar with the J1850 specification
before reading this protocol handler description.
Freescale Semiconductor, Inc.
For More Information On This Product,
Byte Data Link Controller – Digital (BDLC–D)
Go to: www.freescale.com
Figure 14-13. BDLC Block Diagram
PHYSICAL INTERFACE
PROTOCOL HANDLER
MUX INTERFACE
CPU INTERFACE
TO J1850 BUS
TO CPU
BDLC
MC68HC705V12
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Rev. 3.0