mc68hc705v12 Freescale Semiconductor, Inc, mc68hc705v12 Datasheet - Page 170

• Manufacturer Part Number: mc68hc705v12
• Description: M68hc05-based Mcu Hc05 Freescale Semiconductor
• Manufacturer: Freescale Semiconductor, Inc

Byte Data Link Controller – Digital (BDLC–D)
Advance Information
IE— Interrupt Enable Bit
defines the basic timing resolution of the MUX interface. They may be
written only once after reset, after which they become read-only bits.
The nominal frequency of f
MHz for J1850 bus communications to take place. Hence, the value
programmed into these bits is dependent on the chosen MCU system
clock frequency per
This bit determines whether the BDLC will generate CPU interrupt
requests in run mode. It does not affect CPU interrupt requests when
exiting the BDLC stop or BDLC wait modes. Interrupt requests will be
maintained until all of the interrupt request sources are cleared by
performing the specified actions upon the BDLC’s registers. Interrupts
that were pending at the time that this bit is cleared may be lost.
If the programmer does not wish to use the interrupt capability of the
BDLC, the BDLC state vector register (BSVR) can be polled
periodically by the programmer to determine BDLC states. See
BDLC State Vector Register
Freescale Semiconductor, Inc.
1. Invalid option on this MCU
f
For More Information On This Product,
Byte Data Link Controller – Digital (BDLC–D)
1 = Enable interrupt requests from BDLC
0 = Disable interrupt requests from BDLC
XCLK
4.194 MHz
8.389 MHz
4.000 MHz
8.000 MHz
1.049 MHz
2.097 MHz
1.000 MHz
2.000 MHz
Frequency
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(1)
(1)
(1)
(1)
Table 14-3. BDLC Rate Selection
Table
R1
0
0
1
1
0
0
1
1
BDLC
14-3.
for a description of the BSVR.
must always be 1.048576 MHz or 1.0
R0
0
1
0
1
0
1
0
1
Division
MC68HC705V12
1
2
4
8
1
2
4
8
1.049 MHz
1.049 MHz
1.049 MHz
1.049 MHz
1.00 MHz
1.00 MHz
1.00 MHz
1.00 MHz
f
BDLC
—
Rev. 3.0
14.7.4