peb20534h-52 Infineon Technologies Corporation, peb20534h-52 Datasheet - Page 113

• Manufacturer Part Number: peb20534h-52
• Description: Dma Supported Serial Communication Controller With 4 Channels
• Manufacturer: Infineon Technologies Corporation

PEB 20534
PEF 20534
Multi Function Port (MFP)
6.1.3
PCI to Local Bus Bridge Operation
The local bus can work in 8/16-bit multiplexed/de-multiplexed mode. This 8/16-bit
organized address space can be mapped into the host memory space using the base
address register BAR2 in the PCI Configuration Space which is initialized as part of the
device configuration. Other configuration parameters define the clock speed of the local
bus, and the number of wait states on local bus transactions.
PCI accesses to this mapped address range result in the assertion of the chip select
output LCSO and the corresponding write or read transaction is performed on the local
bus.
Register Write to Peripherals:
A PCI write within the local bus address space causes the address and data to be
transferred to the peripherals on the local bus.
The DSCC4 will store a single data DWORD (with correct byte enable information) and
then immediately terminate the PCI transaction successfully (posted write). The write
transaction on the local bus is performed and terminated depending on the selected
number of wait states and the LRDY bus control signal.
The PCI 32-bit addresses are automatically modified to appropriate 16 or 8-bit local bus
addresses.
Thus write accesses to LBI are performed as ‘posted write’ transactions from the PCI
view. A consecutive write transaction results in PCI retry cycles in the case that the
preceding write transaction is not yet finished on the local bus.
With this approach, consecutive PCI writes are possible to the local bus address range.
Register Read from Peripherals:
The local bus address space is mapped into the shared memory space, and hence a
read operation is similar to a read from memory or any memory mapped register within
the PCI address space.
A PCI Retry sequence of operations is performed, in which the DSCC4 will immediately
terminate the PCI transaction (and request a retry) until it terminates the transaction to
the LBI. The DSCC4 uses the retry procedure because the time to complete the data
phase will require more than the maximum allowed 16 PCI clocks (from the assertion of
FRAME to the completion of the first data phase). Data transfer will be successfully
completed within a PCI retry cycle. The number of necessary PCI retry cycles depend
on PCI arbitration behavior and the time it needs to terminate the transaction on the local
bus.
Within the local bus, the PCI read address is physically mapped into the 8/16-bit address
space of the local bus, and the read cycle is performed to the peripheral. A 8/16 bit data
read takes place at the selected local bus speed, and the 8/16 bit data is then passed on
to the PCI cycle with the correct number of C/BE (byte enable) bits set.
Data Sheet
113
2000-05-30