peb20534h-52 Infineon Technologies Corporation, peb20534h-52 Datasheet - Page 321

• Manufacturer Part Number: peb20534h-52
• Description: Dma Supported Serial Communication Controller With 4 Channels
• Manufacturer: Infineon Technologies Corporation

Data Sheet
SRC
TMD
Clock Source
This bit selects the clock source of the internal timer:
SRC = ’0’
SRC = ’1’
Timer Mode
This bit selects between internal and external timer operation mode:
TMD=’0’
TMD=’1’
The timer is clocked by the effective transmit clock.
The timer is clocked by the frame-sync synchronization
signal supplied via the CD pin in clock mode 5.
(Valid in clock mode 5 only.)
External timer mode:
The timer is controlled by the CPU via access to registers
CMDR and TIMR.
The timer can be started any time by setting bit ’STI’ in
register CMDR. The timer stops automatically after it has
expired and generates a timer interrupt. The timer can be
stopped any time by writing zero to the value bit field.
Internal timer mode: (valid in HDLC Automode only)
The timer is used by the DSCC4 for protocol specific time-
out and retry transactions.
321
Detailed Register Description
(HDLC mode)
PEB 20534
PEF 20534
(all modes)
2000-05-30