peb20534h-52 Infineon Technologies Corporation, peb20534h-52 Datasheet - Page 88

• Manufacturer Part Number: peb20534h-52
• Description: Dma Supported Serial Communication Controller With 4 Channels
• Manufacturer: Infineon Technologies Corporation

Table 16
Offset
Addr.
0034
Data Sheet
H
Access
Type
r/w
Bit-Fields
Pos.
31..24,
23..16,
15..8,
7..0
Central FIFO Control Registers (cont’d)
Controlled
by
CPU
Name
TFF
THRESH0,
TFF
THRESH1,
TFF
THRESH2,
TFF
THRESH3,
Reset
Value
00000000
Default
0,
0,
0,
0
88
H
Register Name
FIFOCR4:
FIFO Control Register 4
Description
Transmit FIFO Forward Threshold i
(i=0..3)
Transmit FIFO Forward Threshold for
corresponding channel i in DWORDs. A
watermark is calculated by:
watermark = TFFTHRESHi
As soon as the number of valid data
belonging to a new frame in the transmit
FIFO is greater than the watermark, the
DMAC will provide transmit data to the
corresponding
started a frame the DMAC will ignore this
threshold providing all available data to
the SCC. Threshold operation starts
again with the beginning of a new frame.
Frames shorter than the threshold will be
transferred as soon as a frame end
indication is detected by the DMAC.
Note: The maximum allowed Transmit
Note: Programming TFFTHRESHi to
DMA Controller and Central FIFOs
FIFO Forward Threshold is:
TFFTHRESHi = (TFSIZEi * 4) - 1
zero will disable the threshold
causing the DMAC to transfer all
data immediately. This may be
useful with non packet oriented
data e.g. in ASYNC protocol
mode.
SCC.
Once
PEB 20534
PEF 20534
2000-05-30
having