peb20534h-52 Infineon Technologies Corporation, peb20534h-52 Datasheet - Page 175

• Manufacturer Part Number: peb20534h-52
• Description: Dma Supported Serial Communication Controller With 4 Channels
• Manufacturer: Infineon Technologies Corporation

Figure 63
For transmission of I-frames (selected via bit ’SXIF’ in register CCR2), the address and
control fields are generated autonomously by the SCC and the data in the corresponding
transmit data buffer is entered into the information field of the frame. This is possible only
if the SCC is operated in auto mode.
For (address) transparent frames, the address and the control fields have to be entered
in the transmit data buffer by software. This is possible in all operating modes and used
also in auto-mode for sending U-frames.
If bit ’XCRC’ in register CCR2 is set, the CRC checksum will not be generated internally.
The checksum has to be provided via the transmit data buffer as the last two or four bytes
by software. The transmitted frame will be closed automatically only with a (closing) flag.
Data Sheet
option 2)
Generation of the 16 or 32 bit CRC field can optionally be disabled by setting
bit 'XCRC' in register CCR2, in which case the CRC must be calculated and
written into the last 2 or 4 bytes of the transmit FIFO, to immediately proceed
closing flag.
All Frames with automatic 8 or 16 bit Address and Control Byte Processing
(Auto Mode):
Frames without automatic Address and Control Byte Processing
(Non-Auto Mode, Address Mode 0, 1):
registers
involved
SCC Transmit Data Flow (HDLC Modes)
TFIFO
TFIFO
FLAG
FLAG
ADDR
XAD1
8 bit
16 bitADDR
data
XAD2
CTRL
CRC16
175
data
optional 2)
/32
CRC16
Detailed Protocol Description
FLAG
optional 2)
/32
FLAG
PEB 20534
PEF 20534
2000-05-30