peb20534h-52 Infineon Technologies Corporation, peb20534h-52 Datasheet - Page 32

• Manufacturer Part Number: peb20534h-52
• Description: Dma Supported Serial Communication Controller With 4 Channels
• Manufacturer: Infineon Technologies Corporation

Table 1
Pin No.
35
24
Data Sheet
Symbol
PAR
FRAME
PCI Bus Interface(DEMUX Interface) (cont’d)
Input (I)
Output (O)
t/s
s/t/s
Function
Parity
PAR is even parity across AD(31:0) and C/
BE(3:0). PAR is stable and valid one clock
after the address phase. PAR has the same
timing as AD(31:0) but delayed by one clock.
When DSCC4 is Master, PAR is output during
address phase and write data phases. When
DSCC4 is Slave, PAR is output during read
data phases.
Parity errors detected by the DSCC4 are
indicated on PERR output.
PAR is updated and sampled on the rising
edge of CLK.
Note: PAR is not generated in DEMUX mode
Frame
FRAME indicates the beginning and end of an
access. FRAME is asserted to indicate a bus
transaction is beginning. While FRAME is
asserted, data transfers continue. When
FRAME is deasserted, the transaction is in the
final phase.
When DSCC4 is Master, FRAME is an output.
When DSCC4 is Slave, FRAME is an input.
FRAME is updated and sampled on the rising
edge of CLK.
32
and remains ’0’.A Pull-Down resistor to
V
SS
is recommended.
Pin Descriptions
PEB 20534
PEF 20534
2000-05-30