peb20534h-52 Infineon Technologies Corporation, peb20534h-52 Datasheet - Page 73

• Manufacturer Part Number: peb20534h-52
• Description: Dma Supported Serial Communication Controller With 4 Channels
• Manufacturer: Infineon Technologies Corporation

Table 14
4
(written by
DMAC)
5
(written by
DMAC)
In details the DMA controller reads a receive buffer descriptor, calculates the maximum
data buffer size and the data buffer address and transfers data up to the burst size from
the receive FIFO into the data buffer. For a frame longer than the burst size, this
operation is repeated as long as data is available in the FIFO. For more information
about FIFO control see
After the data buffer has been filled, the controller writes the number of stored bytes into
the descriptor, marks the descriptor “completed” and branches to the next descriptor.
When a frame end (HDLC) or block end (e.g. termination character or time out in ASYNC
mode) is detected and all data has been transferred, the DMA controller writes the
Frame End Descriptor Pointer to the descriptor containing the beginning of the frame. A
maskable interrupt status entry is written into the interrupt queue, if initiated by the host.
As a last transaction the DMA controller writes the number of bytes stored in the last
buffer as well as a DMA controller related status byte in the descriptor.
The DMA controller related status byte indicates, if the frame or block was ended
normally or by a receiver reset command or by a HOLD bit in the current descriptor.
Data Sheet
FE
C
BNO
STATUS
FE Descr Ptr
Receive Descriptor Bit Field Description (cont’d)
Chapter
Frame End Indication:
This bit set to ’1’ indicates that this descriptor contains
a complete data packet or the last part of a data packet.
An ’FI’ interrupt is generated after completion of a
receive descriptor with FE=’1’ setting.
Complete Bit:
This bit is set by the DMAC after having completed the
descriptor and corresponding data section.
The software can use this indication for memory and
linked list management.
Note: The Frame End Descriptor Pointer (DWORD 5) is
Number Of Valid Bytes:
This bit field indicates the number of valid bytes stored
in the receive data buffer upon completion.
Receive Status. Refer to
Frame End Descriptor Pointer:
This address is only written to the first descriptor of a
data packet pointing to the descriptor containing the
’FE’ indication of the same packet. If the complete
packet is stored in the first and only data section this
address is equal to the descriptor address.
5.2).
written to the receive descriptor after writing the
Complete Bit indication to DWORD 4.
73
DMA Controller and Central FIFOs
Page 379
for details.
PEB 20534
PEF 20534
2000-05-30