peb20534h-52 Infineon Technologies Corporation, peb20534h-52 Datasheet - Page 71

• Manufacturer Part Number: peb20534h-52
• Description: Dma Supported Serial Communication Controller With 4 Channels
• Manufacturer: Infineon Technologies Corporation

5.1.2.2
Each receive descriptor consists of 5 consecutive DWORDs, located DWORD aligned
in the shared memory. The first 3 DWORDs are read by the corresponding DMA channel
using a burst transaction and provide information about the buffer size as well as some
control bits, the next descriptor in the linked list and the attached receive data buffer.
The fourth DWORD is written by the DMA channel indicating that operation on this
descriptor is finished. The fifth DWORD is also written by the DMA channel but only in
descriptors containing the first or only data section of an HDLC frame or data block. It is
a pointer to the last descriptor containing the frame or block end (’FE’ bit) allowing the
software to unchain the complete partial descriptor list containing one frame or block
without parsing through the list for ’FE’ indication. It is written after the frame has been
completely written to the shared memory.
The CPU will write the address of the first descriptor of each linked list to a dedicated
Base Address Register during initialization procedure. The corresponding DMA
channels start operating the linked lists at these addresses.
Figure 15
Data Sheet
DMAC Receive Descriptor Lists
Receive Descriptor List Structure
DWORD1
DWORD2
DWORD3
DWORD4
(DWORD5)
Receive Descriptor:
Receive Data Buffer:
31
FE
31
0 Hold HI
byte11
byte15
byte19
byte3
byte7
C
Next Receive Descriptor Pointer
Frame End Descriptor Pointer
0
Receive Data Pointer
byte10
byte14
byte2
byte6
BNO
NO
STATUS
71
byte1
byte5
byte9
0x0000
byte0
byte4
byte8
0x00
DMA Controller and Central FIFOs
0
0
written by
CPU
written by
DSCC4
0
Hold HI
PEB 20534
PEF 20534
2000-05-30