peb20534h-52 Infineon Technologies Corporation, peb20534h-52 Datasheet - Page 344

• Manufacturer Part Number: peb20534h-52
• Description: Dma Supported Serial Communication Controller With 4 Channels
• Manufacturer: Infineon Technologies Corporation

Data Sheet
XOFF
TIN
CSC
XMR
XOFF Character Detected Interrupt
ASYNC Mode:
This bit is set to ’1’, if the currently received character matched the XOFF
character programmed in bit field ’XOFF’ in register XNXF and indicates,
that the transmitter is switched to XOFF-state if in-band flow control is
enabled via bit ’FLON’ in register CCR2.
Timer Interrupt
This bit is set to ’1’, if the internal timer was activated and has expired
(refer also to description of timer register TIMR).
CTS Status Change
This bit is set to ’1’, if a transition occurs on signal CTS. The current state
of signal CTS is monitored by status bit ’CTS’ in status register STAR.
Transmit Message Repeat
HDLC Mode:
This bit is set to ’1’, if transmission of the last frame has to be repeated
(by software), because
• the SCC has received a negative acknowledge to an I-frame in HDLC
• a collision occured after at least four bytes of data has been
• CTS signal was deasserted after at least four bytes of data has been
Note: For easy recovery from a collision event (in bus configuration
BISYNC Mode:
This bit is set to ’1’, if transmission of the last block of characters has to
be repeated (by software), because CTS signal was deasserted after at
least four bytes of data has been completely sent out.
Automode operation;
completely sent out, i.e. automatic re-transmission cannot be
performed by the SCC;
completely sent out.
only), the SCC transmit FIFO should not contain more than one
complete frame. This can be achieved by using the ’ALLS’
interrupt to control the corresponding DMA controller transmit
channel forwarding a new frame on all sent (ALLS) event only.
344
Detailed Register Description
(hdlc/bisync modes)
(async mode)
PEB 20534
PEF 20534
(all modes)
(all modes)
2000-05-30