peb20534h-52 Infineon Technologies Corporation, peb20534h-52 Datasheet - Page 192

• Manufacturer Part Number: peb20534h-52
• Description: Dma Supported Serial Communication Controller With 4 Channels
• Manufacturer: Infineon Technologies Corporation

sampled. Oversampling (3 samples) around the nominal bit center in conjunction with
majority decision is provided for every received bit (including start bit).
The synchronization lasts for one character, the next incoming character causes a new
synchronization to be performed. As a result, the demand for high clock accuracy is
reduced. Two communication stations using the asynchronous procedure are clocked
independently, their clocks need not be in phase or locked to exactly the same frequency
but, in fact, may differ from one another within a certain range.
8.2.2.2
Prerequisites:
• Bit clock rate 1 selected (register CCR0 bit BCR = ‘0’)
• Clock mode 2, 3a, 6, or 7a (DPLL mode) has to be used in conjunction with FM0, FM1
The isochronous mode uses the asynchronous character format. However, each data bit
is only sampled once (no oversampling).
In clock modes 0 and 1, the input clock has to be externally phase locked to the data
stream. This mode allows much higher transfer rates. Clock modes 3b, 4 and 7b are not
recommended due to difficulties with bit synchronization when using the internal baud
rate generator.
In clock modes 2, 3a, 6, and 7a, clock recovery is provided by the internal DPLL. Correct
synchronization of the DPLL is achieved if there are enough edges within the data
stream, which is generally ensured only if Bi-Phase encoding (FM0, FM1 or Manchester)
is used.
8.2.2.3
If the receiver is enabled, received data is stored in the SCC receive FIFO (the LSB is
received first). Moreover, the CD input may be used to control data reception. Character
length, number of stop bits and the optional parity bit are checked. Storage of parity bits
can be disabled. Errors are indicated via interrupts. Additionally, the character specific
error status (framing and parity) can optionally be stored in the SCC receive FIFO.
Filling of the the SCC receive FIFO is controlled by
• a programmable threshold level (bit field ’RFTH’ in register CCR2),
• the selected data format (bit ’RFDF’ in register CCR2),
• the parity storage selection (bit ’DPS’ in register CCR2),
• detection of the programmable Termination Character (bit ’TCDE’ and bit field ’TC’ in
Additionally, the time-out event interrupt as an optional status information indicates that
a certain time (refer to register CCR1) has elapsed since the reception of the last
character.
Data Sheet
or Manchester encoding (register CCR0 bit fields ’CM’ and ’SC’).
register TCR).
Isochronous Mode
Storage of Receive Data
192
Detailed Protocol Description
PEB 20534
PEF 20534
2000-05-30