peb20534h-52 Infineon Technologies Corporation, peb20534h-52 Datasheet - Page 374

• Manufacturer Part Number: peb20534h-52
• Description: Dma Supported Serial Communication Controller With 4 Channels
• Manufacturer: Infineon Technologies Corporation

11
11.1
11.1.1
Each transmit descriptor consists of 4 consecutive DWORDs located DWORD aligned
in the shared memory. The first 3 DWORDs are read by the corresponding DMA channel
using a burst transaction and provide information about the next descriptor in the linked
list, the attached transmit data buffer and its size as well as some control bits.
The fourth DWORD is written by the DMA channel indicating that operation on this
descriptor is finished.
The CPU will write the address of the first descriptor of each linked list to a dedicated
Base Address Register during initialization procedure. The corresponding DMA
channels start operating the linked lists at these addresses.
Figure 77
11.1.1.1 Transmit Descriptor
The transmit descriptor lists are prepared by the host within the shared memory and read
by DSCC4 DMA controller, when requested to do by the host either via an ’AR’ (Action
Request) command or an transmit poll command or after branching from previous
transmit descriptors. The handling of transmit descriptor lists is described in details in
Data Sheet
Host Memory Organization
Linked List Structure
Transmit Descriptor Lists
Transmit Descriptor List Structure
DWORD1
DWORD2
DWORD3
DWORD4
(DWORD5)
Transmit Descriptor:
Transmit Data Buffer:
31
FE Hold HI
31
0
byte11
byte15
byte19
byte3
byte7
C
Next Transmit Descriptor Pointer
0
Transmit Data Pointer
0
byte10
byte14
byte2
byte6
NO
(dummy)
374
byte1
byte5
byte9
0x0000000
0x0000
byte0
byte4
byte8
0
0
Host Memory Organization
FE Hold HI
written by
CPU
written by
DSCC4
PEB 20534
PEF 20534
2000-05-30