peb20534h-52 Infineon Technologies Corporation, peb20534h-52 Datasheet - Page 251

• Manufacturer Part Number: peb20534h-52
• Description: Dma Supported Serial Communication Controller With 4 Channels
• Manufacturer: Infineon Technologies Corporation

Table 50
CPU Accessibility:
Reset Value:
Offset Address:
typical usage:
Data Sheet
Bit 31
Bit 15
IQSCCi
TXBAR
30
14
IQSCCiTXBAR:
Interrupt Queue SCCi Receiver Base Address Register (i=0...3)
i = 3...0
These registers determine the base address of the respective transmit
interrupt queue and can be located anywhere in the 32 bit address
range.
Note: The interrupt queue base addresses must be 32-bit aligned, i.e. bit
29
13
28
12
1 and 0 must be set to ’0’.
read/write
0000 0000
Channel 0
0024
written by CPU
evaluated by DSCC4
27
11
H
IQSCCiTXBAR(15:2)
26
10
H
IQSCCiTXBAR(31:16)
0028
Channel 1
25
9
H
24
251
8
23
7
Channel 2
002C
22
6
H
Detailed Register Description
21
5
20
4
Channel 3
0030
19
(TX Channel 3...0)
3
H
18
2
PEB 20534
PEF 20534
2000-05-30
17
1
0
16
0
0