peb20534h-52 Infineon Technologies Corporation, peb20534h-52 Datasheet - Page 281

• Manufacturer Part Number: peb20534h-52
• Description: Dma Supported Serial Communication Controller With 4 Channels
• Manufacturer: Infineon Technologies Corporation

Data Sheet
SYNC
RFNE
CD
RLI
Synchronization Status
Indicates whether the receiver is in synchronized state. After a ’HUNT’
command ’SYNC’ bit is cleared and the receiver starts searching for a
SYNC character. When found the ’SYNC’ status bit is set immediately,
an SCD-interrupt is generated (if enabled) and receive data is forwarded
to the receive FIFO.
SYNC=’0’
SYNC=’1’
(SCC) Receive FIFO Not Empty
This status bit is set if the SCC receive FIFO stores at least one valid
byte which might be not transferred to the central RFIFO because the
programmed threshold level is not exceeded and no frame end/ block
end condition is generated.
RFNE=’0’
RFNE=’1’
CD (Carrier Detect) Input Signal State
CD=’0’
CD=’1’
Note: A receive clock must be provided in order to detect the signal state
Receive Line Inactive
This bit indicates that neither flags as interframe time fill nor data are
received via the receive line.
RLI=’0’
RLI=’1’
of the CD pin.
Optionally this input can be programmed to generate an interrupt
on signal level changes.
Synchronization is lost or not yet achieved.
(after reset, after new ’HUNT’ command has been issued
before SYNC character is found)
The receiver is in synchronized state.
SCC receive FIFO is empty.
SCC receive FIFO is not empty.
CD input signal is inactive (low level)
CD input signal is active (high level)
Receive line is active, no constant high level is detected.
Receive line is inactive, i.e. more than 7 consecutive ’1’
are detected on the line.
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Detailed Register Description
(async/bisync modes)
(bisync mode)
PEB 20534
PEF 20534
(hdlc mode)
(all modes)
2000-05-30