peb20534h-52 Infineon Technologies Corporation, peb20534h-52 Datasheet - Page 161

• Manufacturer Part Number: peb20534h-52
• Description: Dma Supported Serial Communication Controller With 4 Channels
• Manufacturer: Infineon Technologies Corporation

BISYNC: Transmitter and SCC transmit FIFO are reset and pin TxD goes to ‘1’. The
XMR interrupt is provided which requests the microprocessor to repeat the whole
message or block of characters.
ASYNC: Bus configuration is not recommended.
Note: If a wired-OR connection has been realized by an external pull-up resistor without
7.7.3
To ensure that all competing stations are given a fair access to the transmission medium.
Once a station has successfully completed the transmission of a frame, it is given a lower
level of priority. This priority mechanism is based on the requirement that a station may
attempt transmitting only when a determined number of consecutive ‘1’s are detected on
the bus.
Normally, a transmission can start when eight consecutive ‘1’s on the bus are detected
(through pin CxD). When an HDLC frame has been successfully transmitted, the internal
priority class is decreased. Thus, in order for the same station to be able to transmit
another frame, ten consecutive ‘1’s on the bus must be detected. This guarantees that
the transmission requests of other stations are satisfied before the same station is
allowed a second bus access. When ten consecutive ‘1’s have been detected,
transmission is allowed again and the priority class (of all stations) is increased (to eight
‘1’s).
Inside a priority class, the order of transmission (individual priority) is based on the HDLC
address, as explained in the preceding paragraph. Thus, when a collision occurs, it is
always the station transmitting the only ‘zero’ (i.e. all other stations transmit a ‘one’) in a
bit position of the address field that wins, all other stations cease transmission
immediately.
7.7.4
If a bus configuration has been selected, the SCC provides two timing modes, differing
in the time interval between sending data and evaluation of the transmitted data for
collision detection.
• Timing mode 1 (CCR0:SC1, SC0 = ‘01’)
Data Sheet
Data is output with the rising edge of the transmit clock via the TxD pin, and evaluated
1/2 a clock period later at the CxD pin with the falling clock edge.
decoupling, the data output (TxD) can be used as an open drain output and
connected directly to the CxD input.
For correct identification as to which frame is aborted and thus has to be repeated
after an XMR interrupt has occurred, the contents of SCC transmit FIFO have to
be unique, i.e. SCC transmit FIFO as well as the central transmit FIFO should not
contain data of more than one frame. For this purpose new data my be provided
to the DMA controller only after ’ALLS’ interrupt status is detected.
Serial Bus Access Priority Scheme
Serial Bus Configuration Timing Modes
Serial Communication Controller (SCC) Cores
161
PEB 20534
PEF 20534
2000-05-30