peb20534h-52 Infineon Technologies Corporation, peb20534h-52 Datasheet - Page 203

• Manufacturer Part Number: peb20534h-52
• Description: Dma Supported Serial Communication Controller With 4 Channels
• Manufacturer: Infineon Technologies Corporation

9.2
The first step of initialization is done already via hardware configuration. If DEMUX pin
is connected to
Otherwise (DEMUX connected to
MFP is available as LBI port (Reset state).
After hardware reset, the host has to write a minimum set of registers to initialize the
functional blocks. The following tables provide initialization sequences assuming that in
parallel the host will reserve/prepare memory space for interrupt ring buffers and linked
list data structures before activating the DSCC4’s DMAC by setting GCMDR.AR (See
“Start of Operation” on Page
operating in slave mode.
Table 27
Step
1
2
3
4
5
6
Data Sheet
Action
Select Little-/Big-Endian mode via bit GMODE.ENDIAN.
Select Burst-/No-Burst mode via bit GMODE.DBE.
(Valid only in DEMUX mode)
Select Priority Scheme via bit GMODE.SPRI and
GMODE.CHN.
Configure MFP via bit fields GMODE.PERCFG and
GMODE.LCD as:
- LD15..0, LA15...0 (LBI mux/demux)
- LD15..0, GP 15...8, LA7...0 (GPP + LBI)
- LD15..0, GP15...8, SSC (GPP + SSC + LBI)
- LD15..0, GP15...0 (GPP + LBI)
Set interrupt queue base addresses in registers
IQSCCnRXBAR, IQSCCnTXBAR, IQCFGBAR, IQPBAR
Set interrupt queue lengths in registers
IQLENR1, IQLENR2
Initialization Example
Global Configuration of DSCC4 and Initialization of DMAC (Interrupt
Channel)
V
DD3
, the DSCC4 is configured in de-multiplexed bus interface mode.
207). During the initialization phase the DSCC4 is
V
SS
) the DSCC4 is configured in PCI mode and the
203
Reset and Initialization Procedure
In parallel
reserve memory
space for
interrupt queues
(ring buffers) in
shared memory
PEB 20534
PEF 20534
2000-05-30