peb20534h-52 Infineon Technologies Corporation, peb20534h-52 Datasheet - Page 186

• Manufacturer Part Number: peb20534h-52
• Description: Dma Supported Serial Communication Controller With 4 Channels
• Manufacturer: Infineon Technologies Corporation

8.1.9.4
Similar to the zero bit insertion (bit stuffing) mechanism, as defined by the HDLC
protocol, the SCC offers a completely new feature of inserting/deleting a ’one’ after
seven consecutive ‘zeros’ into the transmit/receive data stream, if the serial channel is
operating in bus configuration mode. This method is useful if clock recovery is performed
by DPLL.
Since only NRZ data encoding is supported in a bus configuration, there are possibly
long sequences without edges in the receive data stream in case of successive ‘0’s
received, and the DPLL may lose synchronization.
Enabling the one bit insertion feature by setting bit ’OIN’ in register CCR2, it is
guaranteed that at least after
– 5 consecutive ‘1’s a ‘0’ will appear (bit stuffing), and after
– 7 consecutive ‘0’s a ‘1’ will appear (one insertion)
and thus a correct function of the DPLL is ensured.
Note: As with the bit stuffing, the ‘one insertion’ is fully transparent to the user, but it is
8.1.9.5
If enabled via bit ’EPT’ in register CCR2, a programmable 8-bit pattern is transmitted with
a selectable number of repetitions after Interframe Timefill transmission is stopped and
a new frame is ready to be sent out. The 8 bit preamble pattern can be programmed in
bit field ’PRE’ and the repetition time in bit field ’PREREP’ of register CCR2.
Note: Zero Bit Insertion is disabled during preamble transmission. To guarantee correct
8.1.9.6
In HDLC/SDLC mode, error protection is done by CRC generation and checking.
In standard applications, CRC-CCITT algorithm is used. The Frame Check Sequence at
the end of each frame consists of two bytes of CRC checksum.
If required, the CRC-CCITT algorithm can be replaced by the CRC-32 algorithm,
enabled via bit ’C32’ in register CCR1. In this case the Frame Check Sequence consists
of four bytes.
As an option in non-auto mode or address mode 0, the internal handling of received and
transmitted CRC checksum can be influenced via control bits ’RCRC’ and ’XCRC’ in
register CCR2.
Data Sheet
not in accordance with the HDLC protocol, i.e. it can only be applied in proprietary
systems using circuits that also implement this function, such as the SAB 82525/
SAB 82526.
function the programmed preamble value should be different from Receive
Address Byte values defined for any of the connected stations.
One Bit Insertion
Preamble Transmission
CRC Generation and Checking
186
Detailed Protocol Description
PEB 20534
PEF 20534
2000-05-30