peb20534h-52 Infineon Technologies Corporation, peb20534h-52 Datasheet - Page 376

• Manufacturer Part Number: peb20534h-52
• Description: Dma Supported Serial Communication Controller With 4 Channels
• Manufacturer: Infineon Technologies Corporation

FE:
HOLD:
NO:
Data Sheet
Frame End, set by the host
It indicates that the current transmit data section (addressed by Transmit
Data Pointer) contains the end of a frame (HDLC, PPP) or the end of data
block (ASYNC, BISYNC). When transferring the last data from this transmit
data section into the internal FIFO the DMAC marks these data with an
’frame end / block end’ indication bit.
GMODE.CMOD=’0’:
After that it checks the HOLD bit stored in the on-chip memory. If HOLD=’0’,
it branches to the next transmit descriptor. Otherwise the corresponding
DMAC transmit channel is deactivated as long as the host CPU does not
request reactivation via the GCMDR register (either transmit poll request or
action request with ’IDT’ command).
GMODE.CMOD=’1’:
After that it checks if the first (current) transmit descriptor address (LTDA) is
equal to the last transmit descriptor address (LTDA) stored in the
corresponding channel specific on-chip registers. When both addresses
differ, it branches to the next transmit descriptor. Otherwise the
corresponding DMAC transmit channel is deactivated as long as the host
CPU does not write a new LTDA value to LTDA register or provides an
action request with ’IDT’ command.
Hold (only valid when GMODE.CMODE=0)
It indicates whether the current descriptor is the last element of a linked list
or not:
Byte Number
This byte number defines the number of bytes stored in the data section to
be transmitted. Thus the maximum length of data buffer is 8191 bytes (i.e.
NO = 1FFF
must contain at least either one data byte or a frame end indication. Other-
wise an DMA controller interrupt with ’ERR’ bit set is generated.
HOLD=’0’: A next descriptor is available in the shared memory; after
HOLD=’1’: The current descriptor is the last one that is available for the
H
). A transmit descriptor and the corresponding data section
checking the HOLD bit stored in the on-chip memory the
DMAC branches to next transmit descriptor
DMAC. The corresponding DMAC channel is deactivated for
transmit direction as long as the microprocessor does not
request an activation via the CMDR register.
376
Host Memory Organization
PEB 20534
PEF 20534
2000-05-30