DS2151 Dallas Semiconducotr, DS2151 Datasheet - Page 13

• Manufacturer Part Number: DS2151
• Description: T1 Single-Chip Transceiver
• Manufacturer: Dallas Semiconducotr

DS2151Q
(with any BPVs that might have occurred intact) via the TTIP and TRING pins. Data will continue to
pass through the receive side of the DS2151Q as it would normally and the data at the TSER input will be
ignored. Data in this loopback will pass through the jitter attenuator. RLB is used to place the DS2151Q
into “line” loopback which is a requirement of both ANSI T1.403 and AT&T TR62411. Please see the
DS2151Q Block Diagram in Section 1 for more details.
PAYLOAD LOOPBACK
When CCR1.1 is set to a 1, the DS2151Q will be forced into Payload LoopBack (PLB). Normally, this
loopback is only enabled when ESF framing is being performed. In a PLB situation, the DS2151Q will
loop the 192 bits of payload data (with BPVs corrected) from the receive section back to the transmit
section. The FPS framing pattern, CRC6 calculation, and the FDL bits are not looped back, they are
reinserted by the DS2151Q. When PLB is enabled, the following will occur:
1. Data will be transmitted from the TTIP and TRING pins synchronous with RCLK instead of TCLK.
2. All of the receive side signals will continue to operate normally.
3. The TCHCLK and TCHBLK signals are forced low.
4. Data at the TSER pin is ignored.
5. The TLCLK signal will become synchronous with RCLK instead of TCLK.
FRAMER LOOPBACK
When CCR1.0 is set to a 1, the DS2151Q will enter a Framer LoopBack (FLB) mode. This loopback is
useful in testing and debugging applications. In FLB, the DS2151Q will loop data from the transmit side
back to the receive side. When FLB is enabled, the following will occur:
1. Unless the RLB is active, an unframed all 1s code will be transmitted at TTIP and TRING.
2. Data off the T1 line at RTIP and RRING will be ignored.
3. The RCLK output will be replaced with the TCLK input.
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