DS2151 Dallas Semiconducotr, DS2151 Datasheet - Page 33

• Manufacturer Part Number: DS2151
• Description: T1 Single-Chip Transceiver
• Manufacturer: Dallas Semiconducotr

12.1 Receive Clock and Data Recovery
The DS2151Q contains a digital clock recovery system. See the DS2151Q Block Diagram in Section 1
and Figure 12-1 for more details. The DS2151Q couples to the receive T1 twisted pair via a 1:1
transformer. See Table 12-3 for transformer details. The DS2151Q automatically adjusts to the T1 signal
being received at the RTIP and RRING pins and can handle T1 lines from 0 feet to over 6000 feet in
length. The crystal attached at the XTAL1 and XTAL2 pins is multiplied by 4 via an internal PLL and
fed to the clock recovery system. The clock recovery system uses both edges of the clock from the PLL
circuit to form a 32 times oversampler which is used to recover the clock and data. This oversampling
technique offers outstanding jitter tolerance (see Figure 12-2). The EGL bit in the Line Interface Control
Register is used to limit the sensitivity of the receiver in the DS2151Q. For most CPE applications, a
receiver sensitivity of -30 dB is wholly sufficient and hence the EGL bit should be set to 1. In some
applications, more sensitivity than -30 dB may be required and the DS2151Q will allow the receiver to go
as low as -36 dB if the EGL bit is set to 0. However, when the EGL bit is set to 0, the DS2151Q will be
more susceptible to crosstalk and its jitter tolerance will suffer.
Normally, the clock that is output at the RCLK pin is the recovered clock from the T1 AMI waveform
presented at the RTIP and RRING inputs. When no AMI signal is present at RTIP and RRING, a
Receive Carrier Loss (RCL) condition will occur and the RCLK can be sourced from either the ACLKI
pin or from the crystal attached to the XTAL1 and XTAL2 pins. The DS2151Q will sense the ACLKI
pin to determine if a clock is present. If no clock is applied to the ACLKI pin, then it should be tied to
RVSS to prevent the device from falsely sensing a clock. See Table 12-1. If the jitter attenuator is either
placed in the transmit path or is disabled, the RCLK output can exhibit short high cycles of the clock.
This is due to the highly oversampled digital clock recovery circuitry. If the jitter attenuator is placed in
the receive path (as is the case in most applications), the jitter attenuator restores the RCLK to being close
to 50% duty cycle. Please see the Receive AC Timing Characteristics in Section 14 for more details.
SOURCE OF RCLK UPON RCL Table 12-1
12.2 Transmit Waveshaping and Line Driving
The DS2151Q uses a set of laser-trimmed delay lines along with a precision Digital-to-Analog Converter
(DAC) to create the waveforms that are transmitted onto the T1 line. The waveforms created by the
DS2151Q meet the latest ANSI, AT&T, and CCITT specifications. See Figure 12-3. The user will select
which waveform is to be generated by properly programming the L0 to L2 bits in the Line Interface
Control Register (LICR).
ACLKI PRESENT?
Yes
No
TPD
LICR.0
ACLKI via the jitter attenuator
RECEIVE SIDE JITTER
ATTENUATOR
centered crystal
1=jitter attenuator disabled
Transmit Power Down.
0=normal transmitter operation
1=powers down the transmitter and 3-states the TTIP and
TRING pins
33 of 51
TRANSMIT SIDE JITTER
TCLK via the jitter attenuator
ATTENUATOR
ACLKI
DS2151Q