DS2151 Dallas Semiconducotr, DS2151 Datasheet - Page 5

• Manufacturer Part Number: DS2151
• Description: T1 Single-Chip Transceiver
• Manufacturer: Dallas Semiconducotr

PIN
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
SYMBOL TYPE
TCHBLK
TSYNC
XTAL1
XTAL2
TLCLK
ACLKI
RRING
TRING
TLINK
DVDD
RVDD
TVDD
RVSS
TVSS
RTIP
TTIP
BTS
INT1
INT2
I/O
O
O
O
O
I
I
-
-
-
-
-
-
-
-
I
-
Alternate Clock Input. Upon a receive carrier loss, the clock applied at
this pin (normally 1.544 MHz) will be routed to the RCLK pin. If no
clock is routed to this pin, then it should be tied to DVSS VIA A1K Ohm
RESISTOR.
Bus Type Select. Strap high to select Motorola bus timing; strap low to
select Intel bus timing. This pin controls the function of the
ALE(AS), and
function listed in parenthesis ().
Receive Tip and Ring. Analog inputs for clock recovery circuitry;
connects to a 1:1 transformer (see Section 12 for details).
Receive Analog Positive Supply. 5.0 volts. Should be tied to DVDD
and TVDD pins.
Receive Signal Ground. 0.0 volts. Should be tied to local ground plane
Crystal Connections. A pullable 6.176 MHz crystal must be applied to
these pins. See Section 12 for crystal specifications.
Receive Alarm Interrupt 1.
conditions defined in Status Register 1. Active low, open drain output.
Receive Alarm Interrupt 2. Flags host controller during conditions
defined in Status Register 2. Active low, open drain output.
Transmit Tip.
transformer (see Section 12 for details).
Transmit Signal Ground. 0.0 volts. Should be tied to local ground
plane.
Transmit Analog Positive Supply. 5.0 volts. Should be tied to DVDD
and RVDD pins.
Transmit Ring.
transformer (see Section 12 for details).
Transmit Channel Block. A user programmable output that can be
forced high or low during any of the 24 T1 channels. Useful for blocking
clocks to a serial UART or LAPD controller in applications where not all
T1 channels are used such as Fractional T1, 384k bps service, 768k bps,
or ISDN-PRI. Also useful for locating individual channels in drop-and-
insert applications. See Section 13 for timing details.
Transmit Link Clock. 4 kHz or 2 kHz (ZBTSI) demand clock for the
TLINK input. See Section 13 for timing details.
Transmit Link Data. If enabled via TCR1.2, this pin will be sampled
during the F-bit time on the falling edge of TCLK for data insertion into
either the FDL stream (ESF) or the Fs bit position (D4) or the Z-bit
position (ZBTSI). See Section 13 for timing details.
Transmit Sync.
multiframe boundaries for the DS2151Q. Via TCR2.2, the DS2151Q can
be programmed to output either a frame or multiframe pulse at this pin. If
this pin is set to output pulses at frame boundaries, it can also be set via
TCR2.4 to output double-wide pulses at signaling frames. See Section 13
for timing details.
Digital Positive Supply. 5.0 volts. Should be tied to RVDD and TVDD
pins.
WR
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Analog line driver output; connects to a step-up
A pulse at this pin will establish either frame or
Analog line driver outputs; connects to a step-up
(R/
W
) pins. If BTS=1, then these pins assume the
DESCRIPTION
Flags host controller during alarm
RD
DS2151Q
(DS),