DS2151 Dallas Semiconducotr, DS2151 Datasheet - Page 20

• Manufacturer Part Number: DS2151
• Description: T1 Single-Chip Transceiver
• Manufacturer: Dallas Semiconducotr

NOTE:
1. The definition of Blue Alarm (or Alarm Indication Signal) is an unframed all 1s signal. Blue alarm
LOOP UP/DOWN CODE DETECTION
Bits SR1.7 and SR1.6 will indicate when either the standard Loop Up or Loop Down codes are being
received by the DS2151Q. When a Loop Up code has been received for 5 seconds, the CPE is expected
to loop the recovered data (without correcting BPVs) back to the source. The Loop Down code indicates
that the loopback should be discontinued. See the AT&T publication TR 62411 for more details. The
DS2151Q will detect the Loop Up/Down codes in both framed and unframed circumstances with bit error
rates as high as 10**-2. The loop code detector has a nominal integration period of 48 ms. Hence, after
about 48 ms of receiving either code, the proper status bit will be set to a 1. After this initial indication, it
is recommended that the software poll the DS2151Q every 100 ms to 500 ms until 5 seconds have elapsed
to insure that the code is continuously present. Once 5 seconds have passed, the DS2151Q should be
taken into or out of loopback via the Remote Loopback (RLB) bit in CCR1.
SR2: STATUS REGISTER 2 (Address=21 Hex)
(MSB)
detectors should be able to operate properly in the presence of a 10-3 error rate and they should not
falsely trigger on a framed all 1s signal. The blue alarm criteria in the DS2151Q has been set to
achieve this performance. It is recommended that the RBL bit be qualified with the RLOS status bit
in detecting a blue alarm.
RMF
SYMBOL POSITION NAME AND DESCRIPTION
RMTCH
RFDL
TFDL
TMF
RMF
TMF
RAF
SEC
-
SR2.7
SR2.6
SR2.5
SR2.4
SR2.3
SR2.2
SR2.1
SR2.0
SEC
Receive Multiframe. Set on receive multiframe boundaries.
Transmit Multiframe. Set on transmit multiframe boundaries.
One Second Timer. Set on increments of 1 second based on
RCLK; will be set in increments of 999 ms, 999 ms, and 1002
ms every 3 seconds.
Receive FDL Buffer Full. Set when the receive FDL buffer
(RFDL) fills to capacity (8 bits).
Transmit FDL Buffer Empty. Set when the transmit FDL
buffer (TFDL) empties.
Receive FDL Match Occurrence.
matches either RFDLM1 or RFDLM2.
Receive FDL Abort.
received in the FDL.
Not Assigned. Should be set to 0 when written.
RFDL
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TFDL
Set when eight consecutive 1s are
RMTCH
Set when the RFDL
RAF
(LSB)
DS2151Q
-