DS2151 Dallas Semiconducotr, DS2151 Datasheet - Page 30

• Manufacturer Part Number: DS2151
• Description: T1 Single-Chip Transceiver
• Manufacturer: Dallas Semiconducotr

9.0 CLOCK BLOCKING REGISTERS
The Receive Channel Blocking Registers (RCBR1/RCBR2/RCBR3) and the Transmit Channel Blocking
Registers (TCBR1/TCBR2/TCBR3) control the RCHBLK and TCHBLK pins respectively.
RCHBLK and TCHCLK pins are user-programmable outputs that can be forced either high or low during
individual channels. These outputs can be used to block clocks to a UART or LAPD controller in
Fractional T1 or ISDN-PRI applications. When the appropriate bits are set to a 1, the RCHBLK and
TCHCLK pins will be held high during the entire corresponding channel time. See the timing in Section
13 for an example.
RCBR1/RCBR2/RCBR3: RECEIVE CHANNEL BLOCKING REGISTERS
(Address=6C to 6E Hex)
TCBR1/TCBR2/TCBR3: TRANSMIT CHANNEL BLOCKING REGISTERS
(Address=32 to 34 Hex)
10.0 ELASTIC STORES OPERATION
The DS2151Q has two onboard two-frame (386 bits) elastic stores. These elastic stores have two main
purposes.
2.048 Mbps), which is the E1 rate. Secondly, they can be used to absorb the differences in frequency and
phase between the T1 data stream and an asynchronous (i.e., not frequency locked) backplane clock.
Both elastic stores contain full controlled slip capability which is necessary for this second purpose. The
receive side elastic store can be enabled via CCR1.2 and the transmit side elastic store is enabled via
CCR1.7. The elastic stores can be forced to a known depth via the Elastic Store Reset bit (CCR3.6).
(MSB)
(MSB)
CH16
CH24
CH16
CH24
CH8
CH8
First, they can be used to rate-convert the T1 data stream to 2.048 Mbps (or a multiple of
CH15
CH23
CH7
CH15
CH23
CH7
SYMBOL POSITION NAME AND DESCRIPTION
SYMBOL POSITION NAME AND DESCRIPTION
CH24
CH24
CH14
CH22
CH1
CH1
CH6
CH14
CH22
CH6
RCBR3.7
RCBR1.0
TCBR3.7
TCBR1.0
CH13
CH21
CH13
CH21
CH5
CH5
Receive Channel Blocking Registers
0=force the RCHBLK pin to remain low during this
channel time
1=force the RCHBLK pin high during this channel time
Transmit Channel Blocking Registers.
0=force the TCHBLK pin to remain low during this
channel time
1=force the TCHBLK pin high during this channel time
CH12
CH20
CH4
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CH12
CH20
CH4
CH11
CH19
CH11
CH19
CH3
CH3
CH10
CH18
CH10
CH18
CH2
CH2
(LSB)
CH17
(LSB)
CH17
CH1
CH9
CH1
CH9
RCBR2 (6D)
RCBR1 (6C)
RCBR3 (6E)
TCBR1 (32)
TCBR2 (33)
TCBR3 (34)
DS2151Q
The