DS2151 Dallas Semiconducotr, DS2151 Datasheet - Page 15

• Manufacturer Part Number: DS2151
• Description: T1 Single-Chip Transceiver
• Manufacturer: Dallas Semiconducotr

CCR3: COMMON CONTROL REGISTER 3 (Address=30 Hex)
LOOP CODE GENERATION
When either the CCR3.1 or CCR3.2 bits are set to 1, the DS2151Q will replace the normal transmitted
payload with either the Loop Up or Loop Down code respectively.
repeating loop code pattern with the framing bits. The SCT will continue to transmit the loop codes as
long as either bit is set. It is an illegal state to have both CCR3.1 and CCR3.2 set to 1 at the same time.
ESMDM
(MSB)
SYMBOL POSITION NAME AND DESCRIPTION
ESMDM
LIRST
RSMS
ESR
P16F
PDE
TLD
TLU
ESR
CCR3.7
CCR3.6
CCR3.5
CCR3.4
CCR3.3
CCR3.2
CCR3.1
CCR3.0
P16F
Elastic Store Minimum Delay Mode. See Section 10.3 for
details.
0=elastic stores operate at full two-frame depth
1=elastic stores operate at 32-bit depth
Elastic Store Reset. Setting this bit from a 0 to a 1 will force
the elastic stores to a known depth. Should be toggled after
SYSCLK has been applied and is stable. Must be cleared and
set again for a subsequent reset.
Function of Pin 16.
0=Receive Loss of Sync (RLOS).
1=Loss of Transmit Clock (LOTC).
RSYNC Multiframe Skip Control. Useful in framing format
conversions from D4 to ESF.
0=RSYNC will output a pulse at every multiframe
1=RSYNC will output a pulse at every other multiframe note:
for this bit to have any affect, the RSYNC must be set to output
multiframe pulses (RCR2.4=1 and RCR2.3=0) and the receive
elastic store must be bypassed. (CCR1.2 = 0).
Pulse Density Enforcer Enable.
0=disable transmit pulse density enforcer
1=enable transmit pulse density enforcer
Transmit Loop Down Code (001).
0=transmit data normally
1=replace normal transmitted data with Loop Down code
Transmit Loop Up Code (00001).
0=transmit data normally
1=replace normal transmitted data with Loop Up code
Line Interface Reset. Setting this bit from a 0 to a one will
initiate an internal reset that affects the slicer, AGC, clock
recovery state machine and jitter attenuator. Normally this bit is
only toggled on power-up. Must be cleared and set again for a
subsequent reset.
RSMS
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PDE
TLD
The DS2151Q will overwrite the
TLU
LIRST
(LSB)
DS2151Q