DS2151 Dallas Semiconducotr, DS2151 Datasheet - Page 41

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DS2151

Manufacturer Part Number
DS2151
Description
T1 Single-Chip Transceiver
Manufacturer
Dallas Semiconducotr
Datasheet

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TRANSMIT SIDE ESF TIMING Figure 13-7
NOTES:
1. TSYNC in the frame mode (TCR2.3=0) and double-wide frame sync is not enabled (TCR2.4=0).
2. TSYNC in the frame mode (TCR2.3=0) and double-wide frame sync is enabled (TCR2.4=1).
3. TSYNC in the multiframe mode (TCR2.4=1).
4. ZBTSI mode disabled (TCR2.5=0).
5. TLINK data (FDL bits) is sampled during the F-bit time of odd frame and inserted into the outgoing
6. ZBTSI mode is enabled (TCR2.5=1).
7. TLINK data (Z bits) is sampled during the F-bit time of frame 1, 5, 9, 13, 17, and 21 and inserted into
T1 stream if enabled via TCR1.2.
the outgoing stream if enabled via TCR1.2.
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DS2151Q

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