DS2151 Dallas Semiconducotr, DS2151 Datasheet - Page 4

• Manufacturer Part Number: DS2151
• Description: T1 Single-Chip Transceiver
• Manufacturer: Dallas Semiconducotr

PIN DESCRIPTION Table 1-1
PIN
10
11
12
13
14
15
16
17
18
8
1
2
3
4
5
6
7
9
RLOS/LOTC
SYMBOL
WR
RCHCLK
RCHBLK
ALE(AS)
SYSCLK
RD
RLCLK
RSYNC
RLINK
RCLK
DVSS
RSER
AD4
AD5
AD6
AD7
CS
(R/
(DS)
W
)
TYPE
I/O
I/O
O
O
O
O
O
O
O
I
I
I
I
-
I
Address/Data Bus. An 8-bit multiplexed address/data bus.
Read Input (Data Strobe).
Chip Select. Must be low to read or write the port.
Address Latch Enable (Address Strobe). A positive going edge
serves to demultiplex the bus.
Write Input (Read/Write).
Receive Link Data. Updated with either FDL data (ESF) or Fs bits
(D4) or Z bits (ZBTSI) one RCLK before the start of a frame. See
Section 13 for timing details.
Receive Link Clock. 4 kHz or 2 kHz (ZBTSI) demand clock for the
RLINK output. See Section 13 for timing details.
Digital Signal Ground. 0.0 volts. Should be tied to local ground plane.
Receive Clock. Recovered 1.544 MHz clock.
Receive Channel Clock. 192 kHz clock which pulses high during the
LSB of each channel. Useful for parallel to serial conversion of channel
data, locating Robbed-Bit signaling bits, and for blocking clocks in
DDS applications. See Section 13 for timing details.
Receive Serial Data. Received NRZ serial data, updated on rising
edges of RCLK or SYSCLK.
Receive Sync. An extracted pulse, one RCLK wide, is output at this
pin which identifies either frame (RCR2.4=0) or multiframe boundaries
(RCR2.4=1). If set to output frame boundaries, then via RCR2.5,
RSYNC can also be set to output double-wide pulses on signaling
frames. If the elastic store is enabled via the CCR1.2, then this pin can
be enabled to be an input via RCR2.3 at which a frame boundary pulse
is applied. See Section 13 for timing details.
Receive Loss of Sync/Loss of Transmit Clock. A dual function
output. If CCR3.5=0, will toggle high when the synchronizer is
searching for the T1 frame and multiframe; if CCR3.5=1, will toggle
high if the TCLK pin has not toggled for 5 us.
System Clock. 1.544 MHz or 2.048 MHz clock. Only used when the
elastic store functions are enabled via either CCR1.7 or CCR1.2.
Should be tied low in applications that do not use the elastic store. If
tied high for more than 100 us, will force all output pins (including the
parallel port) to 3-state.
Receive Channel Block. A user programmable output that can be
forced high or low during any of the 24 T1 channels. Useful for
blocking clocks to a serial UART or LAPD controller in applications
where not all T1 channels are used such as Fractional T1, 384k bps
service, 768k bps, or ISDN-PRI. Also useful for locating individual
channels in drop-and-insert applications. See Section 13 for timing
details.
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DESCRIPTION
DS2151Q